AU2006277451A1 - Write protection method of sequential access semiconductor storage device - Google Patents

Write protection method of sequential access semiconductor storage device Download PDF

Info

Publication number
AU2006277451A1
AU2006277451A1 AU2006277451A AU2006277451A AU2006277451A1 AU 2006277451 A1 AU2006277451 A1 AU 2006277451A1 AU 2006277451 A AU2006277451 A AU 2006277451A AU 2006277451 A AU2006277451 A AU 2006277451A AU 2006277451 A1 AU2006277451 A1 AU 2006277451A1
Authority
AU
Australia
Prior art keywords
write
data
address
area
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2006277451A
Other languages
English (en)
Inventor
Noboru Asauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of AU2006277451A1 publication Critical patent/AU2006277451A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/06—Apparatus for electrographic processes using a charge pattern for developing
    • G03G15/08—Apparatus for electrographic processes using a charge pattern for developing using a solid developer, e.g. powder developer
    • G03G15/0822—Arrangements for preparing, mixing, supplying or dispensing developer
    • G03G15/0863—Arrangements for preparing, mixing, supplying or dispensing developer provided with identifying means or means for storing process- or use parameters, e.g. an electronic memory
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G2215/00—Apparatus for electrophotographic processes
    • G03G2215/06—Developing structures, details
    • G03G2215/066—Toner cartridge or other attachable and detachable container for supplying developer material to replace the used material
    • G03G2215/0695—Toner cartridge or other attachable and detachable container for supplying developer material to replace the used material using identification means or means for storing process or use parameters
    • G03G2215/0697—Toner cartridge or other attachable and detachable container for supplying developer material to replace the used material using identification means or means for storing process or use parameters being an electronically readable memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)
  • Ink Jet (AREA)
AU2006277451A 2005-08-10 2006-07-26 Write protection method of sequential access semiconductor storage device Abandoned AU2006277451A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005-231503 2005-08-10
JP2005231503 2005-08-10
PCT/JP2006/315259 WO2007018084A1 (fr) 2005-08-10 2006-07-26 Procédé de protection contre l’écriture de dispositif de stockage semi-conducteur à accès séquentiel

Publications (1)

Publication Number Publication Date
AU2006277451A1 true AU2006277451A1 (en) 2007-02-15

Family

ID=37727271

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2006277451A Abandoned AU2006277451A1 (en) 2005-08-10 2006-07-26 Write protection method of sequential access semiconductor storage device

Country Status (11)

Country Link
US (1) US7406576B2 (fr)
EP (1) EP1921631A4 (fr)
JP (1) JP4910705B2 (fr)
KR (1) KR20080033531A (fr)
CN (1) CN101243519B (fr)
AU (1) AU2006277451A1 (fr)
BR (1) BRPI0614247A2 (fr)
CA (1) CA2616359A1 (fr)
RU (1) RU2008108626A (fr)
TW (1) TW200717527A (fr)
WO (1) WO2007018084A1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929155B1 (ko) * 2007-01-25 2009-12-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 메모리 셀 억세스 방법
US7929372B2 (en) * 2007-01-25 2011-04-19 Samsung Electronics Co., Ltd. Decoder, memory system, and physical position converting method thereof
JP5170246B2 (ja) * 2008-08-05 2013-03-27 日本電気株式会社 半導体検証装置、方法およびプログラム
JP5233801B2 (ja) * 2009-04-01 2013-07-10 セイコーエプソン株式会社 記憶装置、ホスト回路、基板、液体容器、不揮発性のデータ記憶部に格納されたデータをホスト回路に送信する方法、ホスト回路と、前記ホスト回路と着脱可能な記憶装置を含むシステム
US9141538B2 (en) 2010-07-07 2015-09-22 Marvell World Trade Ltd. Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive
US8868852B2 (en) 2010-07-07 2014-10-21 Marvell World Trade Ltd. Interface management control systems and methods for non-volatile semiconductor memory
US9135168B2 (en) 2010-07-07 2015-09-15 Marvell World Trade Ltd. Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error
US8184487B2 (en) * 2010-08-30 2012-05-22 Micron Technology, Inc. Modified read operation for non-volatile memory
WO2015166494A1 (fr) * 2014-04-29 2015-11-05 Raphael Cohen Circuit intégré d'interception d'adresse pour fonction d'écriture unique d'une mémoire
US9767045B2 (en) * 2014-08-29 2017-09-19 Memory Technologies Llc Control for authenticated accesses to a memory device
CN104354473B (zh) * 2014-09-29 2016-03-30 珠海艾派克微电子有限公司 一种成像盒芯片及成像盒
CN104570653B (zh) * 2014-12-26 2017-10-10 珠海赛纳打印科技股份有限公司 一种图像形成装置及对附加纸盒的控制方法
US10748591B2 (en) 2019-01-13 2020-08-18 Ememory Technology Inc. Random code generator
JP2021006960A (ja) * 2019-06-28 2021-01-21 株式会社アクセル メモリコントローラ、及び、不揮発性記憶装置
US11561707B2 (en) 2021-01-08 2023-01-24 Western Digital Technologies, Inc. Allocating data storage based on aggregate duplicate performance
US12008254B2 (en) * 2021-01-08 2024-06-11 Western Digital Technologies, Inc. Deduplication of storage device encoded data

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60193193A (ja) * 1984-03-13 1985-10-01 Toshiba Corp メモリｌｓｉ
JP3229066B2 (ja) * 1993-04-21 2001-11-12 セイコーインスツルメンツ株式会社 半導体集積回路
KR100319886B1 (ko) * 1999-05-04 2002-01-10 윤종용 외부 어드레스에 의해 자동 리프레쉬 동작이 수행될 수 있는 테스트 모드를 갖는 동기식 디램 및 자동 리프레쉬 방법
JP4497689B2 (ja) 1999-10-01 2010-07-07 キヤノン株式会社 印刷装置、交換ユニット、及び、メモリユニット
US6643751B2 (en) * 2000-03-20 2003-11-04 Texas Instruments Incorporated System and method for limited access to system memory
JP4081963B2 (ja) * 2000-06-30 2008-04-30 セイコーエプソン株式会社 記憶装置および記憶装置に対するアクセス方法
JP2002023570A (ja) * 2000-07-13 2002-01-23 Canon Inc 画像形成装置およびその装置ユニット
US6976136B2 (en) * 2001-05-07 2005-12-13 National Semiconductor Corporation Flash memory protection scheme for secured shared BIOS implementation in personal computers with an embedded controller
US7051180B2 (en) * 2002-01-09 2006-05-23 International Business Machines Corporation Masterless building block binding to partitions using identifiers and indicators
US7295787B2 (en) * 2003-08-22 2007-11-13 Ricoh Company, Ltd. Device unit, an image forming apparatus, a management system, and a recycling system capable of using non-genuine device unit as replacement product

Also Published As

Publication number Publication date
BRPI0614247A2 (pt) 2011-03-15
KR20080033531A (ko) 2008-04-16
JP4910705B2 (ja) 2012-04-04
WO2007018084A1 (fr) 2007-02-15
CA2616359A1 (fr) 2007-02-15
CN101243519B (zh) 2010-10-13
US7406576B2 (en) 2008-07-29
US20070050584A1 (en) 2007-03-01
EP1921631A1 (fr) 2008-05-14
CN101243519A (zh) 2008-08-13
RU2008108626A (ru) 2009-09-20
JPWO2007018084A1 (ja) 2009-02-19
TW200717527A (en) 2007-05-01
EP1921631A4 (fr) 2009-03-11

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Legal Events

Date Code Title Description
MK5 Application lapsed section 142(2)(e) - patent request and compl. specification not accepted