AU2002234101A1 - Non-integral multiple size array loop processing in simd architecture - Google Patents

Non-integral multiple size array loop processing in simd architecture

Info

Publication number
AU2002234101A1
AU2002234101A1 AU2002234101A AU3410102A AU2002234101A1 AU 2002234101 A1 AU2002234101 A1 AU 2002234101A1 AU 2002234101 A AU2002234101 A AU 2002234101A AU 3410102 A AU3410102 A AU 3410102A AU 2002234101 A1 AU2002234101 A1 AU 2002234101A1
Authority
AU
Australia
Prior art keywords
integral multiple
loop processing
multiple size
size array
simd architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002234101A
Inventor
John L. Redford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipWrights Design Inc
Original Assignee
ChipWrights Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ChipWrights Design Inc filed Critical ChipWrights Design Inc
Publication of AU2002234101A1 publication Critical patent/AU2002234101A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
AU2002234101A 2000-11-13 2001-11-09 Non-integral multiple size array loop processing in simd architecture Abandoned AU2002234101A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09711556 2000-11-13
US09/711,556 US6732253B1 (en) 2000-11-13 2000-11-13 Loop handling for single instruction multiple datapath processor architectures
PCT/US2001/050029 WO2002039271A1 (en) 2000-11-13 2001-11-09 Non-integral multiple size array loop processing in simd architecture

Publications (1)

Publication Number Publication Date
AU2002234101A1 true AU2002234101A1 (en) 2002-05-21

Family

ID=24858560

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002234101A Abandoned AU2002234101A1 (en) 2000-11-13 2001-11-09 Non-integral multiple size array loop processing in simd architecture

Country Status (8)

Country Link
US (2) US6732253B1 (en)
JP (1) JP2004513455A (en)
KR (1) KR20030072354A (en)
CN (1) CN1484786A (en)
AU (1) AU2002234101A1 (en)
DE (1) DE10196879T5 (en)
TW (1) TW563063B (en)
WO (1) WO2002039271A1 (en)

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Also Published As

Publication number Publication date
WO2002039271A1 (en) 2002-05-16
JP2004513455A (en) 2004-04-30
DE10196879T5 (en) 2004-04-15
TW563063B (en) 2003-11-21
US20040158691A1 (en) 2004-08-12
US6732253B1 (en) 2004-05-04
KR20030072354A (en) 2003-09-13
CN1484786A (en) 2004-03-24

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