AU2001249122A1 - Processing architecture having field swapping capability - Google Patents

Processing architecture having field swapping capability

Info

Publication number
AU2001249122A1
AU2001249122A1 AU2001249122A AU4912201A AU2001249122A1 AU 2001249122 A1 AU2001249122 A1 AU 2001249122A1 AU 2001249122 A AU2001249122 A AU 2001249122A AU 4912201 A AU4912201 A AU 4912201A AU 2001249122 A1 AU2001249122 A1 AU 2001249122A1
Authority
AU
Australia
Prior art keywords
processing architecture
swapping capability
field
field swapping
capability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001249122A
Inventor
Daniel S. Rice
Ashley Saulsbury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001249122A1 publication Critical patent/AU2001249122A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
AU2001249122A 2000-03-08 2001-03-08 Processing architecture having field swapping capability Abandoned AU2001249122A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US18768500P 2000-03-08 2000-03-08
US60187685 2000-03-08
PCT/US2001/007461 WO2001067235A2 (en) 2000-03-08 2001-03-08 Processing architecture having sub-word shuffling and opcode modification

Publications (1)

Publication Number Publication Date
AU2001249122A1 true AU2001249122A1 (en) 2001-09-17

Family

ID=22690026

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001249122A Abandoned AU2001249122A1 (en) 2000-03-08 2001-03-08 Processing architecture having field swapping capability

Country Status (5)

Country Link
US (1) US6816961B2 (en)
EP (1) EP1261912A2 (en)
AU (1) AU2001249122A1 (en)
HK (1) HK1048539A1 (en)
WO (1) WO2001067235A2 (en)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5742840A (en) 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US7631025B2 (en) * 2001-10-29 2009-12-08 Intel Corporation Method and apparatus for rearranging data between multiple registers
US7725521B2 (en) * 2001-10-29 2010-05-25 Intel Corporation Method and apparatus for computing matrix transformations
US7739319B2 (en) * 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7624138B2 (en) * 2001-10-29 2009-11-24 Intel Corporation Method and apparatus for efficient integer transform
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7013321B2 (en) 2001-11-21 2006-03-14 Sun Microsystems, Inc. Methods and apparatus for performing parallel integer multiply accumulate operations
US7558816B2 (en) 2001-11-21 2009-07-07 Sun Microsystems, Inc. Methods and apparatus for performing pixel average operations
US6981166B2 (en) * 2002-01-07 2005-12-27 International Business Machines Corporation Method, apparatus, and computer program product for pacing clocked operations
US6963341B1 (en) * 2002-06-03 2005-11-08 Tibet MIMAR Fast and flexible scan conversion and matrix transpose in a SIMD processor
US7315261B2 (en) * 2003-07-02 2008-01-01 Texas Instruments Incorporated Method for converting data from pixel format to bitplane format
GB2409059B (en) * 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
GB2409061B (en) * 2003-12-09 2006-09-13 Advanced Risc Mach Ltd Table lookup operation within a data processing system
GB2409066B (en) * 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
US7376813B2 (en) * 2004-03-04 2008-05-20 Texas Instruments Incorporated Register move instruction for section select of source operand
US7418582B1 (en) 2004-05-13 2008-08-26 Sun Microsystems, Inc. Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7509484B1 (en) 2004-06-30 2009-03-24 Sun Microsystems, Inc. Handling cache misses by selectively flushing the pipeline
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
JP2008513903A (en) * 2004-09-21 2008-05-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Microprocessor device and method for shuffle operations
US7761694B2 (en) 2006-06-30 2010-07-20 Intel Corporation Execution unit for performing shuffle and other operations
JP2008047031A (en) * 2006-08-21 2008-02-28 Kumamoto Univ Concurrent computing device
US20090292908A1 (en) * 2008-05-23 2009-11-26 On Demand Electronics Method and arrangements for multipath instruction processing
US20110072236A1 (en) * 2009-09-20 2011-03-24 Mimar Tibet Method for efficient and parallel color space conversion in a programmable processor
KR101699685B1 (en) * 2010-11-16 2017-01-26 삼성전자 주식회사 Apparatus and method for changing instruction operand
JP5988222B2 (en) * 2011-10-18 2016-09-07 パナソニックＩｐマネジメント株式会社 Shuffle pattern generation circuit, processor, shuffle pattern generation method, instruction
US20130339656A1 (en) * 2012-06-15 2013-12-19 International Business Machines Corporation Compare and Replace DAT Table Entry
EP2851786A1 (en) * 2013-09-23 2015-03-25 Telefonaktiebolaget L M Ericsson (publ) Instruction class for digital signal processors
US10296334B2 (en) * 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit gather
US20160188333A1 (en) * 2014-12-27 2016-06-30 Intel Coporation Method and apparatus for compressing a mask value
US10459731B2 (en) * 2015-07-20 2019-10-29 Qualcomm Incorporated Sliding window operation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293907A (en) * 1978-12-29 1981-10-06 Bell Telephone Laboratories, Incorporated Data processing apparatus having op-code extension register
JPS5858653A (en) * 1981-10-02 1983-04-07 Hitachi Ltd Data processor
US5446865A (en) * 1990-03-13 1995-08-29 At&T Corp. Processor adapted for sharing memory with more than one type of processor
US5687338A (en) 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
WO1997044739A1 (en) * 1996-05-23 1997-11-27 Advanced Micro Devices, Inc. Apparatus for converting data between different endian formats and system and method employing same
US5900011A (en) 1996-07-01 1999-05-04 Sun Microsystems, Inc. Integrated processor/memory device with victim data cache
US5909572A (en) * 1996-12-02 1999-06-01 Compaq Computer Corp. System and method for conditionally moving an operand from a source register to a destination register
US5890009A (en) * 1996-12-12 1999-03-30 International Business Machines Corporation VLIW architecture and method for expanding a parcel
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6675182B1 (en) * 2000-08-25 2004-01-06 International Business Machines Corporation Method and apparatus for performing rotate operations using cascaded multiplexers

Also Published As

Publication number Publication date
HK1048539A1 (en) 2003-04-04
WO2001067235A2 (en) 2001-09-13
US6816961B2 (en) 2004-11-09
WO2001067235A3 (en) 2002-04-18
EP1261912A2 (en) 2002-12-04
US20020035678A1 (en) 2002-03-21

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