AU2002222632A1 - Method of etching porous insulating film, dual damascene process, and semiconductor device - Google Patents

Method of etching porous insulating film, dual damascene process, and semiconductor device

Info

Publication number
AU2002222632A1
AU2002222632A1 AU2002222632A AU2263202A AU2002222632A1 AU 2002222632 A1 AU2002222632 A1 AU 2002222632A1 AU 2002222632 A AU2002222632 A AU 2002222632A AU 2263202 A AU2263202 A AU 2263202A AU 2002222632 A1 AU2002222632 A1 AU 2002222632A1
Authority
AU
Australia
Prior art keywords
semiconductor device
insulating film
dual damascene
damascene process
porous insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002222632A
Inventor
Li-Hung Chen
Koichiro Inazawa
Tomoki Suemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of AU2002222632A1 publication Critical patent/AU2002222632A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU2002222632A 2000-12-14 2001-12-13 Method of etching porous insulating film, dual damascene process, and semiconductor device Abandoned AU2002222632A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-380813 2000-12-14
JP2000380813 2000-12-14
PCT/JP2001/010933 WO2002049089A1 (en) 2000-12-14 2001-12-13 Method of etching porous insulating film, dual damascene process, and semiconductor device

Publications (1)

Publication Number Publication Date
AU2002222632A1 true AU2002222632A1 (en) 2002-06-24

Family

ID=18848930

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002222632A Abandoned AU2002222632A1 (en) 2000-12-14 2001-12-13 Method of etching porous insulating film, dual damascene process, and semiconductor device

Country Status (4)

Country Link
JP (1) JPWO2002049089A1 (en)
AU (1) AU2002222632A1 (en)
TW (1) TWI223341B (en)
WO (1) WO2002049089A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004017533A1 (en) * 2003-05-03 2005-01-13 Trikon Technologies Limited, Newport Method for etching porous dielectric
JP4963156B2 (en) * 2003-10-03 2012-06-27 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6949460B2 (en) * 2003-11-12 2005-09-27 Lam Research Corporation Line edge roughness reduction for trench etch
JP4523351B2 (en) * 2004-07-14 2010-08-11 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP4643975B2 (en) * 2004-11-26 2011-03-02 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5103025B2 (en) * 2006-02-10 2012-12-19 九州電通株式会社 Method for removing surface layer of silicon wafer
JP6499001B2 (en) * 2015-04-20 2019-04-10 東京エレクトロン株式会社 Method for etching a porous membrane

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163470A (en) * 1992-11-24 1994-06-10 Sumitomo Metal Ind Ltd Etching method
JP3525788B2 (en) * 1999-03-12 2004-05-10 セイコーエプソン株式会社 Method for manufacturing semiconductor device
JP4207303B2 (en) * 1999-04-07 2009-01-14 ソニー株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TWI223341B (en) 2004-11-01
JPWO2002049089A1 (en) 2004-04-15
WO2002049089A1 (en) 2002-06-20

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