ATE67890T1 - Steuersystem fuer gekettete schaltungsmodule. - Google Patents

Steuersystem fuer gekettete schaltungsmodule.

Info

Publication number
ATE67890T1
ATE67890T1 AT86904286T AT86904286T ATE67890T1 AT E67890 T1 ATE67890 T1 AT E67890T1 AT 86904286 T AT86904286 T AT 86904286T AT 86904286 T AT86904286 T AT 86904286T AT E67890 T1 ATE67890 T1 AT E67890T1
Authority
AT
Austria
Prior art keywords
modules
enabled
write
read
path
Prior art date
Application number
AT86904286T
Other languages
English (en)
Inventor
Michael Brent
Original Assignee
Anamartic Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anamartic Ltd filed Critical Anamartic Ltd
Application granted granted Critical
Publication of ATE67890T1 publication Critical patent/ATE67890T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)
  • Semiconductor Memories (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Non-Volatile Memory (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Vehicle Body Suspensions (AREA)
  • Amplifiers (AREA)
  • Control Of Stepping Motors (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
AT86904286T 1985-07-12 1986-07-11 Steuersystem fuer gekettete schaltungsmodule. ATE67890T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB8517699A GB2177825B (en) 1985-07-12 1985-07-12 Control system for chained circuit modules
PCT/GB1986/000401 WO1987000675A2 (en) 1985-07-12 1986-07-11 Control system for chained circuit modules
EP86904286A EP0231237B1 (de) 1985-07-12 1986-07-11 Steuersystem für gekettete schaltungsmodule

Publications (1)

Publication Number Publication Date
ATE67890T1 true ATE67890T1 (de) 1991-10-15

Family

ID=10582224

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86904286T ATE67890T1 (de) 1985-07-12 1986-07-11 Steuersystem fuer gekettete schaltungsmodule.

Country Status (8)

Country Link
US (1) US4943946A (de)
EP (2) EP0416714A3 (de)
JP (2) JPS63500545A (de)
KR (2) KR880700423A (de)
AT (1) ATE67890T1 (de)
DE (1) DE3681724D1 (de)
GB (3) GB2177825B (de)
WO (1) WO1987000675A2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2184268B (en) * 1985-12-13 1989-11-22 Anamartic Ltd Fault tolerant memory system
EP0424979A3 (en) 1986-03-18 1991-07-03 Anamartic Limited Random address system for circuit modules
GB8713819D0 (en) * 1987-06-12 1987-12-16 Smiths Industries Plc Information processing systems
US4798976A (en) * 1987-11-13 1989-01-17 International Business Machines Corporation Logic redundancy circuit scheme
US5287345A (en) * 1988-02-04 1994-02-15 The City University Data handling arrays
GB9112776D0 (en) * 1991-06-13 1991-07-31 Univ City A wafer scale integrated circuit
US5933608A (en) * 1988-02-04 1999-08-03 The City University Multiway signal switching device including a WSIC and optical communication ports
WO1989012320A1 (en) * 1988-06-01 1989-12-14 Anamartic Limited Wafer scale integrated circuits
JP2516403B2 (ja) * 1988-06-01 1996-07-24 富士通株式会社 ウエハ・スケ―ル・メモリ
KR900003884A (ko) * 1988-08-12 1990-03-27 미다 가쓰시게 대규모 반도체 집적회로 장치
US5347450A (en) * 1989-01-18 1994-09-13 Intel Corporation Message routing in a multiprocessor computer system
US5594866A (en) * 1989-01-18 1997-01-14 Intel Corporation Message routing in a multi-processor computer system with alternate edge strobe regeneration
GB8903181D0 (en) * 1989-02-13 1989-03-30 Anamartic Ltd Improvements relating to control systems for chained circuit modules
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
GB2234372A (en) * 1989-07-18 1991-01-30 Anamartic Ltd Mass memory device
JP2522837B2 (ja) * 1989-09-19 1996-08-07 富士通株式会社 ウエハ・スケ―ル半導体装置
JPH03106029A (ja) * 1989-09-20 1991-05-02 Fujitsu Ltd ウエハ・スケール・ｉｃ
EP0509058A4 (en) * 1990-01-05 1993-11-18 Maspar Computer Corporation Router chip with quad-crossbar and hyperbar personalities
GB2250359A (en) * 1990-11-19 1992-06-03 Anamartic Ltd Addressing of chained circuit modules
US5467428A (en) * 1991-06-06 1995-11-14 Ulug; Mehmet E. Artificial neural network method and architecture adaptive signal filtering
GB9417271D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Memory device
US6230245B1 (en) 1997-02-11 2001-05-08 Micron Technology, Inc. Method and apparatus for generating a variable sequence of memory device command signals
US6175894B1 (en) 1997-03-05 2001-01-16 Micron Technology, Inc. Memory device command buffer apparatus and method and memory devices and computer systems using same
WO1998045787A1 (en) * 1997-04-10 1998-10-15 Advanced Micro Devices, Inc. Pin count reduction through serialization techniques
US5996043A (en) * 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6484244B1 (en) 1997-06-17 2002-11-19 Micron Technology, Inc. Method and system for storing and processing multiple memory commands
US6202119B1 (en) 1997-12-19 2001-03-13 Micron Technology, Inc. Method and system for processing pipelined memory commands
US6175905B1 (en) 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
US6178488B1 (en) 1998-08-27 2001-01-23 Micron Technology, Inc. Method and apparatus for processing pipelined memory commands
EP1050883B1 (de) * 1999-05-03 2006-03-08 STMicroelectronics S.A. Schaltung zur Steuerung der Datenspeicherung
GB2379542B (en) * 2000-09-05 2003-09-10 Samsung Electronics Co Ltd System comprising memory module
US7308524B2 (en) 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
DE10350356B3 (de) * 2003-10-29 2005-02-17 Infineon Technologies Ag Integrierte Schaltung, Testsystem und Verfahren zum Auslesen eines Fehlerdatums aus der integrierten Schaltung
US9727267B1 (en) * 2016-09-27 2017-08-08 Intel Corporation Power management and monitoring for storage devices
US10095432B2 (en) 2016-09-27 2018-10-09 Intel Corporation Power management and monitoring for storage devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US3882470A (en) * 1974-02-04 1975-05-06 Honeywell Inf Systems Multiple register variably addressable semiconductor mass memory
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
US3972031A (en) * 1974-08-15 1976-07-27 Zonic Technical Laboratories, Inc. Variable length shift register alternately operable to store and recirculate data and addressing circuit therefor
US4020469A (en) * 1975-04-09 1977-04-26 Frank Manning Programmable arrays
US4148099A (en) * 1978-04-11 1979-04-03 Ncr Corporation Memory device having a minimum number of pins
GB2082354B (en) * 1980-08-21 1984-04-11 Burroughs Corp Improvements in or relating to wafer-scale integrated circuits
GB2089536B (en) * 1980-12-12 1984-05-23 Burroughs Corp Improvement in or relating to wafer scale integrated circuits
US4528647A (en) * 1981-01-07 1985-07-09 Burroughs Corp. Wafer scale integrated circuit memories
GB2114782B (en) * 1981-12-02 1985-06-05 Burroughs Corp Branched-spiral wafer-scale integrated circuit

Also Published As

Publication number Publication date
KR880700422A (ko) 1988-03-15
GB8517699D0 (en) 1985-08-21
GB2177825B (en) 1989-07-26
DE3681724D1 (de) 1991-10-31
WO1987000675A2 (en) 1987-01-29
EP0231237A1 (de) 1987-08-12
JPS63500618A (ja) 1988-03-03
US4943946A (en) 1990-07-24
GB2177825A (en) 1987-01-28
GB8819599D0 (en) 1988-09-21
WO1987000675A3 (en) 1987-03-26
EP0231237B1 (de) 1991-09-25
GB2207785B (en) 1989-07-26
EP0416714A2 (de) 1991-03-13
JPS63500545A (ja) 1988-02-25
GB2178204A (en) 1987-02-04
EP0416714A3 (en) 1991-08-07
GB2178204B (en) 1988-11-16
GB2207785A (en) 1989-02-08
KR880700423A (ko) 1988-03-15
GB8525324D0 (en) 1985-11-20

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties