ATE61496T1 - Integrierter schaltkreis von neuartiger architektur und sein hertellungsverfahren. - Google Patents

Integrierter schaltkreis von neuartiger architektur und sein hertellungsverfahren.

Info

Publication number
ATE61496T1
ATE61496T1 AT87400496T AT87400496T ATE61496T1 AT E61496 T1 ATE61496 T1 AT E61496T1 AT 87400496 T AT87400496 T AT 87400496T AT 87400496 T AT87400496 T AT 87400496T AT E61496 T1 ATE61496 T1 AT E61496T1
Authority
AT
Austria
Prior art keywords
novel architecture
integrated circuit
manufacturing process
prediffused
macrocells
Prior art date
Application number
AT87400496T
Other languages
English (en)
Inventor
Joseph Borel
Jean Michard
Eric Zardi
Original Assignee
Thomson Semiconducteurs
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Semiconducteurs filed Critical Thomson Semiconducteurs
Application granted granted Critical
Publication of ATE61496T1 publication Critical patent/ATE61496T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/935—Degree of specialisation for implementing specific functions
    • H10D84/937—Implementation of digital circuits
    • H10D84/938—Implementation of memory functions

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
AT87400496T 1986-03-12 1987-03-06 Integrierter schaltkreis von neuartiger architektur und sein hertellungsverfahren. ATE61496T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8603507A FR2595870B1 (fr) 1986-03-12 1986-03-12 Circuit integre avec macrocellules noyees dans une mer de portes de type prediffusees et procede de fabrication
EP87400496A EP0237425B1 (de) 1986-03-12 1987-03-06 Integrierter Schaltkreis von neuartiger Architektur und sein Hertellungsverfahren

Publications (1)

Publication Number Publication Date
ATE61496T1 true ATE61496T1 (de) 1991-03-15

Family

ID=9333041

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87400496T ATE61496T1 (de) 1986-03-12 1987-03-06 Integrierter schaltkreis von neuartiger architektur und sein hertellungsverfahren.

Country Status (5)

Country Link
EP (1) EP0237425B1 (de)
JP (1) JPS62276866A (de)
AT (1) ATE61496T1 (de)
DE (1) DE3768296D1 (de)
FR (1) FR2595870B1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2712079B2 (ja) * 1988-02-15 1998-02-10 株式会社東芝 半導体装置
JP2911946B2 (ja) * 1990-02-15 1999-06-28 日本電気株式会社 集積回路装置
JP7771523B2 (ja) * 2021-04-07 2025-11-18 富士電機株式会社 電力変換装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054334B2 (ja) * 1977-09-27 1985-11-29 旭化成株式会社 熱収縮性架橋ポリエチレン系樹脂フイルムの製造方法
JPS57124463A (en) * 1981-01-26 1982-08-03 Nec Corp Semiconductor device
JPS58137230A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓマスタ・スライスｌｓｉ
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit

Also Published As

Publication number Publication date
EP0237425B1 (de) 1991-03-06
JPS62276866A (ja) 1987-12-01
EP0237425A1 (de) 1987-09-16
DE3768296D1 (de) 1991-04-11
FR2595870A1 (fr) 1987-09-18
FR2595870B1 (fr) 1988-10-14

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Legal Events

Date Code Title Description
EEFA Change of the company name
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee