ATE503271T1 - Verfahren zur herstellung von isolierten integrierten halbleiterstrukturen - Google Patents

Verfahren zur herstellung von isolierten integrierten halbleiterstrukturen

Info

Publication number
ATE503271T1
ATE503271T1 AT08850185T AT08850185T ATE503271T1 AT E503271 T1 ATE503271 T1 AT E503271T1 AT 08850185 T AT08850185 T AT 08850185T AT 08850185 T AT08850185 T AT 08850185T AT E503271 T1 ATE503271 T1 AT E503271T1
Authority
AT
Austria
Prior art keywords
doped
bipolar transistor
region
integrated semiconductor
tank region
Prior art date
Application number
AT08850185T
Other languages
English (en)
Inventor
Scott Blaster
Bahid El-Kareh
Horishi Yasuda
Original Assignee
Texas Instruments Deutschland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Deutschland filed Critical Texas Instruments Deutschland
Application granted granted Critical
Publication of ATE503271T1 publication Critical patent/ATE503271T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AT08850185T 2007-11-15 2008-11-14 Verfahren zur herstellung von isolierten integrierten halbleiterstrukturen ATE503271T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007056103A DE102007056103B4 (de) 2007-11-15 2007-11-15 Verfahren zur Herstellung von isolierten integrierten Halbleiterstrukturen
US12/137,817 US8012842B2 (en) 2007-11-15 2008-06-12 Method for fabricating isolated integrated semiconductor structures
PCT/EP2008/065548 WO2009063046A1 (en) 2007-11-15 2008-11-14 Method for fabricating isolated integrated semiconductor structures

Publications (1)

Publication Number Publication Date
ATE503271T1 true ATE503271T1 (de) 2011-04-15

Family

ID=40576889

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08850185T ATE503271T1 (de) 2007-11-15 2008-11-14 Verfahren zur herstellung von isolierten integrierten halbleiterstrukturen

Country Status (5)

Country Link
US (1) US8012842B2 (de)
EP (1) EP2218100B1 (de)
AT (1) ATE503271T1 (de)
DE (2) DE102007056103B4 (de)
WO (1) WO2009063046A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8896064B2 (en) 2010-10-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection circuit
US8609501B2 (en) 2011-09-09 2013-12-17 Texas Instruments Incorporated Fluorine implant under isolation dielectric structures to improve bipolar transistor performance and matching
US9293357B2 (en) 2012-07-02 2016-03-22 Texas Instruments Incorporated Sinker with a reduced width
KR102140358B1 (ko) * 2016-12-23 2020-08-03 매그나칩 반도체 유한회사 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623159A (en) * 1994-10-03 1997-04-22 Motorola, Inc. Integrated circuit isolation structure for suppressing high-frequency cross-talk
KR100258436B1 (ko) * 1996-10-11 2000-06-01 김덕중 상보형 쌍극성 트랜지스터 및 그 제조 방법
US6586317B1 (en) * 2001-05-08 2003-07-01 National Semiconductor Corporation Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage
US6943426B2 (en) * 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7902630B2 (en) * 2002-08-14 2011-03-08 Advanced Analogic Technologies, Inc. Isolated bipolar transistor
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate

Also Published As

Publication number Publication date
EP2218100A1 (de) 2010-08-18
WO2009063046A1 (en) 2009-05-22
EP2218100B1 (de) 2011-03-23
US20090127630A1 (en) 2009-05-21
DE102007056103A1 (de) 2009-05-28
US8012842B2 (en) 2011-09-06
DE102007056103B4 (de) 2010-03-04
DE602008005793D1 (de) 2011-05-05

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Legal Events

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