ATE490503T1 - Mehrbit-fehlerkorrekturschema in einem speichersystem mit mehreren niveaus - Google Patents

Mehrbit-fehlerkorrekturschema in einem speichersystem mit mehreren niveaus

Info

Publication number
ATE490503T1
ATE490503T1 AT08761407T AT08761407T ATE490503T1 AT E490503 T1 ATE490503 T1 AT E490503T1 AT 08761407 T AT08761407 T AT 08761407T AT 08761407 T AT08761407 T AT 08761407T AT E490503 T1 ATE490503 T1 AT E490503T1
Authority
AT
Austria
Prior art keywords
characteristic parameter
memory cells
bit
value
error correction
Prior art date
Application number
AT08761407T
Other languages
English (en)
Inventor
Chung Lam
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE490503T1 publication Critical patent/ATE490503T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Detection And Correction Of Errors (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
AT08761407T 2007-07-02 2008-07-01 Mehrbit-fehlerkorrekturschema in einem speichersystem mit mehreren niveaus ATE490503T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/772,356 US7966547B2 (en) 2007-07-02 2007-07-02 Multi-bit error correction scheme in multi-level memory storage system
PCT/EP2008/058426 WO2009003995A1 (en) 2007-07-02 2008-07-01 Multi-bit error correction scheme in multi-level memory storage system

Publications (1)

Publication Number Publication Date
ATE490503T1 true ATE490503T1 (de) 2010-12-15

Family

ID=39967757

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08761407T ATE490503T1 (de) 2007-07-02 2008-07-01 Mehrbit-fehlerkorrekturschema in einem speichersystem mit mehreren niveaus

Country Status (7)

Country Link
US (1) US7966547B2 (de)
EP (1) EP2186005B1 (de)
JP (1) JP4588806B2 (de)
KR (1) KR20100033517A (de)
AT (1) ATE490503T1 (de)
DE (1) DE602008003843D1 (de)
WO (1) WO2009003995A1 (de)

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US8839076B2 (en) 2011-03-31 2014-09-16 International Business Machines Corporation Encoding a data word for writing the encoded data word in a multi-level solid state memory
US9021328B2 (en) 2013-01-15 2015-04-28 International Business Machines Corporation Shared error protection for register banks
US9201727B2 (en) 2013-01-15 2015-12-01 International Business Machines Corporation Error protection for a data bus
US9041428B2 (en) 2013-01-15 2015-05-26 International Business Machines Corporation Placement of storage cells on an integrated circuit
US9043683B2 (en) 2013-01-23 2015-05-26 International Business Machines Corporation Error protection for integrated circuits
US9601189B2 (en) 2013-04-24 2017-03-21 Hewlett Packard Enterprise Development Lp Representing data using a group of multilevel memory cells
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US9690640B2 (en) * 2013-09-26 2017-06-27 Intel Corporation Recovery from multiple data errors
US10162702B2 (en) 2016-02-01 2018-12-25 Lattice Semiconductor Corporation Segmented error coding for block-based memory
US10318378B2 (en) * 2016-02-25 2019-06-11 Micron Technology, Inc Redundant array of independent NAND for a three-dimensional memory array
US10402165B2 (en) * 2017-08-30 2019-09-03 Gsi Technology Inc. Concurrent multi-bit adder
DE102019120801B3 (de) * 2019-08-01 2020-12-03 Infineon Technologies Ag Vorrichtungen und Verfahren zur Datenspeicherung
US11916570B1 (en) * 2022-11-11 2024-02-27 Texas Instruments Incorporated Codeword format for data storage

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Also Published As

Publication number Publication date
US20090013223A1 (en) 2009-01-08
EP2186005A1 (de) 2010-05-19
JP4588806B2 (ja) 2010-12-01
WO2009003995A1 (en) 2009-01-08
KR20100033517A (ko) 2010-03-30
DE602008003843D1 (de) 2011-01-13
JP2010534361A (ja) 2010-11-04
US7966547B2 (en) 2011-06-21
EP2186005B1 (de) 2010-12-01

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