ATE476709T1 - Speichersteuerung und verfahren zum schreiben in einen speicher - Google Patents

Speichersteuerung und verfahren zum schreiben in einen speicher

Info

Publication number
ATE476709T1
ATE476709T1 AT03813945T AT03813945T ATE476709T1 AT E476709 T1 ATE476709 T1 AT E476709T1 AT 03813945 T AT03813945 T AT 03813945T AT 03813945 T AT03813945 T AT 03813945T AT E476709 T1 ATE476709 T1 AT E476709T1
Authority
AT
Austria
Prior art keywords
memory
write
register
data
address information
Prior art date
Application number
AT03813945T
Other languages
English (en)
Inventor
Jan Hoogerbrugge
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE476709T1 publication Critical patent/ATE476709T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Communication Control (AREA)
  • Saccharide Compounds (AREA)
  • Steroid Compounds (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT03813945T 2002-12-30 2003-11-26 Speichersteuerung und verfahren zum schreiben in einen speicher ATE476709T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02080598 2002-12-30
PCT/IB2003/005709 WO2004059499A2 (en) 2002-12-30 2003-11-26 Memory controller and method for writing to a memory

Publications (1)

Publication Number Publication Date
ATE476709T1 true ATE476709T1 (de) 2010-08-15

Family

ID=32668869

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03813945T ATE476709T1 (de) 2002-12-30 2003-11-26 Speichersteuerung und verfahren zum schreiben in einen speicher

Country Status (8)

Country Link
US (1) US7568082B2 (de)
EP (1) EP1581876B1 (de)
JP (1) JP2006512657A (de)
CN (1) CN1732446B (de)
AT (1) ATE476709T1 (de)
AU (1) AU2003303412A1 (de)
DE (1) DE60333677D1 (de)
WO (1) WO2004059499A2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
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US7849253B2 (en) * 2005-04-04 2010-12-07 Standard Microsystems Corporation Method for fast access to flash-memory media
JP4791909B2 (ja) * 2006-08-21 2011-10-12 株式会社東芝 高速入出力機能を備える制御装置、及びその制御データの制御方法
JP2008134685A (ja) * 2006-11-27 2008-06-12 Konica Minolta Business Technologies Inc 不揮発メモリシステム及び不揮発メモリ制御方法
CN100499557C (zh) * 2007-06-18 2009-06-10 中兴通讯股份有限公司 一种寻址控制器件及使用该器件进行寻址的方法
US8332575B2 (en) * 2007-06-20 2012-12-11 Samsung Electronics Co., Ltd. Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance
TWI391911B (zh) * 2008-04-15 2013-04-01 Novatek Microelectronics Corp 記憶體存取裝置及使用該記憶體存取裝置的顯示器
KR101631162B1 (ko) * 2009-06-11 2016-06-17 삼성전자주식회사 플래시 메모리를 구비하는 저장 장치 및 이의 데이터 저장 방법
CN101876944B (zh) 2009-11-26 2012-02-15 威盛电子股份有限公司 动态随机存取存储器控制器和控制方法
US8489803B2 (en) * 2009-12-14 2013-07-16 Smsc Holdings S.A.R.L. Efficient use of flash memory in flash drives
US8806263B2 (en) * 2011-08-26 2014-08-12 Micron Technology, Inc. Methods and apparatuses including a global timing generator and local control circuits
JP5727948B2 (ja) 2012-01-16 2015-06-03 株式会社東芝 半導体記憶装置
TWI594251B (zh) * 2012-06-06 2017-08-01 慧榮科技股份有限公司 記憶體控制方法、控制器跟電子裝置
US9417958B2 (en) 2012-06-06 2016-08-16 Silicon Motion Inc. Flash memory control method, controller and electronic apparatus
KR20170048942A (ko) * 2015-10-27 2017-05-10 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10891057B1 (en) * 2015-12-31 2021-01-12 EMC IP Holding Company LLC Optimizing flash device write operations
KR102648180B1 (ko) * 2016-07-19 2024-03-18 에스케이하이닉스 주식회사 메모리 시스템 및 그 동작 방법
CN109426616B (zh) * 2017-08-31 2023-08-04 华邦电子股份有限公司 字节编程方法以及页面编程方法
CN110457198A (zh) * 2018-05-07 2019-11-15 龙芯中科技术有限公司 调试信息输出方法、装置及存储介质
US11393550B2 (en) 2018-09-14 2022-07-19 Rambus Inc. Memory system with error detection
CN112802518B (zh) * 2021-03-25 2021-07-02 深圳市汇顶科技股份有限公司 数据写入方法、片上系统芯片及计算机可读存储介质
CN114546906B (zh) * 2022-01-28 2023-06-23 郑州信大捷安信息技术股份有限公司 一种基于ring通信机制的数据交互方法和系统

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
CN85105547B (zh) * 1985-07-19 1988-06-08 株式会社日立制作所 用于一信息处理装置的存储器存取控制系统
JPS6379292A (ja) * 1986-09-24 1988-04-09 Nec Corp スタテイツク型メモリ
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5553265A (en) * 1994-10-21 1996-09-03 International Business Machines Corporation Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
US5787484A (en) * 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US5835406A (en) 1996-10-24 1998-11-10 Micron Quantum Devices, Inc. Apparatus and method for selecting data bits read from a multistate memory
JPH10154394A (ja) 1996-11-21 1998-06-09 Toshiba Corp メモリ装置
US6438660B1 (en) * 1997-12-09 2002-08-20 Intel Corporation Method and apparatus for collapsing writebacks to a memory for resource efficiency
US6151658A (en) * 1998-01-16 2000-11-21 Advanced Micro Devices, Inc. Write-buffer FIFO architecture with random access snooping capability
JP2001014219A (ja) * 1999-06-30 2001-01-19 Nec Corp キャッシュ制御方法及びその装置
US6678838B1 (en) * 1999-08-23 2004-01-13 Advanced Micro Devices, Inc. Method to track master contribution information in a write buffer
CN1121041C (zh) * 2000-11-27 2003-09-10 英业达集团（南京）电子技术有限公司 在快闪存储器中同时存放程序代码及数据资料的方法
JP3701886B2 (ja) * 2001-04-27 2005-10-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶回路ブロック及びアクセス方法

Also Published As

Publication number Publication date
CN1732446A (zh) 2006-02-08
DE60333677D1 (de) 2010-09-16
WO2004059499A3 (en) 2004-09-02
US20060106969A1 (en) 2006-05-18
EP1581876B1 (de) 2010-08-04
WO2004059499A2 (en) 2004-07-15
JP2006512657A (ja) 2006-04-13
US7568082B2 (en) 2009-07-28
CN1732446B (zh) 2010-09-08
AU2003303412A1 (en) 2004-07-22
EP1581876A2 (de) 2005-10-05

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