ATE473564T1 - Verfahren und schaltung zur initialisierung eines laufzeitausgleichpuffers in einem taktweitergeleiteten system - Google Patents
Verfahren und schaltung zur initialisierung eines laufzeitausgleichpuffers in einem taktweitergeleiteten systemInfo
- Publication number
- ATE473564T1 ATE473564T1 AT02026822T AT02026822T ATE473564T1 AT E473564 T1 ATE473564 T1 AT E473564T1 AT 02026822 T AT02026822 T AT 02026822T AT 02026822 T AT02026822 T AT 02026822T AT E473564 T1 ATE473564 T1 AT E473564T1
- Authority
- AT
- Austria
- Prior art keywords
- buffer
- pointer
- circuit
- read pointer
- read
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/005—Correction by an elastic buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
- G06F2205/104—Delay lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/10—Arrangements for initial synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33679801P | 2001-12-03 | 2001-12-03 | |
US10/044,549 US6952791B2 (en) | 2001-12-03 | 2002-01-11 | Method and circuit for initializing a de-skewing buffer in a clock forwarded system |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE473564T1 true ATE473564T1 (de) | 2010-07-15 |
Family
ID=26721697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT02026822T ATE473564T1 (de) | 2001-12-03 | 2002-11-28 | Verfahren und schaltung zur initialisierung eines laufzeitausgleichpuffers in einem taktweitergeleiteten system |
Country Status (4)
Country | Link |
---|---|
US (1) | US6952791B2 (de) |
EP (1) | EP1317085B1 (de) |
AT (1) | ATE473564T1 (de) |
DE (1) | DE60236913D1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6961861B2 (en) * | 2002-02-27 | 2005-11-01 | Sun Microsystems, Inc. | Globally clocked interfaces having reduced data path length |
US7698588B2 (en) * | 2003-05-15 | 2010-04-13 | International Business Machines Corporation | Circuit and related method for synchronizing data signals to a core clock |
TWI233053B (en) * | 2003-11-06 | 2005-05-21 | Via Tech Inc | Apparatus and method for initializing an elastic buffer |
CN1328668C (zh) * | 2003-11-19 | 2007-07-25 | 威盛电子股份有限公司 | 弹性缓冲器的初始装置及其方法 |
US20100315134A1 (en) * | 2008-02-28 | 2010-12-16 | Nxp B.V. | Systems and methods for multi-lane communication busses |
US9143315B2 (en) * | 2013-10-25 | 2015-09-22 | Advanced Micro Devices, Inc. | Predictive periodic synchronization using phase-locked loop digital ratio updates |
US9250859B2 (en) * | 2014-01-17 | 2016-02-02 | Altera Corporation | Deterministic FIFO buffer |
JP6512640B1 (ja) | 2017-10-19 | 2019-05-15 | Necプラットフォームズ株式会社 | 非同期fifo回路 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2853523C2 (de) * | 1978-12-12 | 1981-10-01 | Ibm Deutschland Gmbh, 7000 Stuttgart | Dezentrale Erzeugung von Taktsteuersignalen |
DE3213345C2 (de) * | 1982-04-08 | 1984-11-22 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen |
JPS63110811A (ja) * | 1986-10-28 | 1988-05-16 | Mitsubishi Electric Corp | クロツクジエネレ−タ |
JPH01251738A (ja) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | スタンダードセル |
US5224129A (en) * | 1990-10-31 | 1993-06-29 | Tektronix, Inc. | Method of synchronizing signals of a pulse generator |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5357613A (en) * | 1992-09-16 | 1994-10-18 | Texas Instruments Incorporated | Time-domain boundary buffer method and apparatus |
US5640605A (en) * | 1994-08-26 | 1997-06-17 | 3Com Corporation | Method and apparatus for synchronized transmission of data between a network adaptor and multiple transmission channels using a shared clocking frequency and multilevel data encoding |
US5768529A (en) * | 1995-05-05 | 1998-06-16 | Silicon Graphics, Inc. | System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers |
US5867731A (en) * | 1996-08-12 | 1999-02-02 | Unisys Corporation | System for data transfer across asynchronous interface |
US5872959A (en) * | 1996-09-10 | 1999-02-16 | Lsi Logic Corporation | Method and apparatus for parallel high speed data transfer |
KR100255664B1 (ko) * | 1997-12-29 | 2000-05-01 | 윤종용 | 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법 |
US6098139A (en) * | 1998-05-27 | 2000-08-01 | 3Com Corporation | Frequency independent asynchronous clock crossing FIFO |
US6067629A (en) * | 1998-08-10 | 2000-05-23 | Intel Corporation | Apparatus and method for pseudo-synchronous communication between clocks of different frequencies |
JP3447586B2 (ja) * | 1998-10-22 | 2003-09-16 | Necエレクトロニクス株式会社 | クロック同期化方法及びその装置 |
US6269413B1 (en) * | 1998-10-30 | 2001-07-31 | Hewlett Packard Company | System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections |
US6370600B1 (en) * | 1999-05-25 | 2002-04-09 | Advanced Micro Devices, Inc. | Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency |
US6434640B1 (en) * | 1999-05-25 | 2002-08-13 | Advanced Micro Devices, Inc. | Unload counter adjust logic for a receiver buffer |
DE19935437C1 (de) * | 1999-07-28 | 2001-04-12 | Siemens Ag | Laufzeitausgleich für einen Invers-Multiplexer |
US6813275B1 (en) * | 2000-04-21 | 2004-11-02 | Hewlett-Packard Development Company, L.P. | Method and apparatus for preventing underflow and overflow across an asynchronous channel |
US6744834B1 (en) * | 2000-04-28 | 2004-06-01 | Hewlett-Packard Company | Method and apparatus for initializing a synchronizer for same frequency, phase unknown data across multiple bit-sliced interfaces |
US6751235B1 (en) * | 2000-06-27 | 2004-06-15 | Intel Corporation | Communication link synchronization method |
US6333893B1 (en) * | 2000-08-21 | 2001-12-25 | Micron Technology, Inc. | Method and apparatus for crossing clock domain boundaries |
-
2002
- 2002-01-11 US US10/044,549 patent/US6952791B2/en not_active Expired - Fee Related
- 2002-11-28 EP EP02026822A patent/EP1317085B1/de not_active Expired - Lifetime
- 2002-11-28 DE DE60236913T patent/DE60236913D1/de not_active Expired - Lifetime
- 2002-11-28 AT AT02026822T patent/ATE473564T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1317085B1 (de) | 2010-07-07 |
EP1317085A2 (de) | 2003-06-04 |
DE60236913D1 (de) | 2010-08-19 |
EP1317085A3 (de) | 2006-02-08 |
US20030105985A1 (en) | 2003-06-05 |
US6952791B2 (en) | 2005-10-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |