ATE495489T1 - Fifo-puffer - Google Patents

Fifo-puffer

Info

Publication number
ATE495489T1
ATE495489T1 AT08776408T AT08776408T ATE495489T1 AT E495489 T1 ATE495489 T1 AT E495489T1 AT 08776408 T AT08776408 T AT 08776408T AT 08776408 T AT08776408 T AT 08776408T AT E495489 T1 ATE495489 T1 AT E495489T1
Authority
AT
Austria
Prior art keywords
circuit
address
write pointer
read
clock
Prior art date
Application number
AT08776408T
Other languages
English (en)
Inventor
Johannes Boonstra
Sundaravaradan Rangarajan
Rajendra Kumar
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE495489T1 publication Critical patent/ATE495489T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Air Bags (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
AT08776408T 2007-05-16 2008-05-14 Fifo-puffer ATE495489T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07108299 2007-05-16
PCT/IB2008/051894 WO2008142610A1 (en) 2007-05-16 2008-05-14 Fifo buffer

Publications (1)

Publication Number Publication Date
ATE495489T1 true ATE495489T1 (de) 2011-01-15

Family

ID=39735570

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08776408T ATE495489T1 (de) 2007-05-16 2008-05-14 Fifo-puffer

Country Status (6)

Country Link
US (1) US8612651B2 (de)
EP (1) EP2149083B1 (de)
CN (1) CN101681249B (de)
AT (1) ATE495489T1 (de)
DE (1) DE602008004500D1 (de)
WO (1) WO2008142610A1 (de)

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US8417982B1 (en) * 2009-08-11 2013-04-09 Marvell Israel (M.I.S.L.) Ltd. Dual clock first-in first-out (FIFO) memory system
TWI504154B (zh) * 2010-07-30 2015-10-11 Realtek Semiconductor Corp 多相位時脈切換裝置與其方法
CN102654827B (zh) * 2011-03-02 2014-05-28 安凯(广州)微电子技术有限公司 一种先进先出缓冲器及缓存数据的方法
CN102880442B (zh) * 2011-07-13 2015-05-27 瑞昱半导体股份有限公司 用于时钟树转换处的先入先出(fifo)装置与方法
CN102495713A (zh) * 2011-12-09 2012-06-13 盛科网络（苏州）有限公司 实现任意深度异步fifo的方法及系统
US9911470B2 (en) 2011-12-15 2018-03-06 Nvidia Corporation Fast-bypass memory circuit
US8924612B2 (en) * 2012-04-04 2014-12-30 Arm Limited Apparatus and method for providing a bidirectional communications link between a master device and a slave device
CN102799410B (zh) * 2012-06-19 2015-03-04 东南大学 基于李氏制约竞争计数编码的异步fifo地址转换电路
CN103632712A (zh) 2012-08-27 2014-03-12 辉达公司 存储单元和存储器
US9685207B2 (en) 2012-12-04 2017-06-20 Nvidia Corporation Sequential access memory with master-slave latch pairs and method of operating
US9281817B2 (en) * 2012-12-31 2016-03-08 Nvidia Corporation Power conservation using gray-coded address sequencing
US10141930B2 (en) 2013-06-04 2018-11-27 Nvidia Corporation Three state latch
US9672008B2 (en) * 2014-11-24 2017-06-06 Nvidia Corporation Pausible bisynchronous FIFO
US9509640B2 (en) * 2014-12-05 2016-11-29 Xilinx, Inc. Latency control in a transmitter/receiver buffer
WO2016203492A2 (en) * 2015-06-16 2016-12-22 Gyan Prakash Method for cycle accurate data transfer in a skewed synchronous clock domain
US10254967B2 (en) 2016-01-13 2019-04-09 Sandisk Technologies Llc Data path control for non-volatile memory
US10528255B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10528267B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Command queue for storage operations
US10528286B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10114589B2 (en) 2016-11-16 2018-10-30 Sandisk Technologies Llc Command control for multi-core non-volatile memory
KR102342547B1 (ko) * 2017-07-12 2021-12-23 삼성전자주식회사 버퍼 컨트롤러, 메모리 장치 및 집적회로 장치
US11010293B1 (en) * 2018-01-23 2021-05-18 Marvell Israel (M.I.S.L) Ltd. Register-based asynchronous FIFO with asymmetric size
US11436166B2 (en) * 2019-02-05 2022-09-06 Arm Limited Data processing systems
US11461030B2 (en) * 2019-07-15 2022-10-04 Micron Technology, Inc. Transferring data between clock domains using pulses across a queue
CN111258533B (zh) * 2020-01-14 2025-11-04 厦门鑫忆讯科技有限公司 任意深度异步fifo存储器
CN111367495B (zh) * 2020-03-06 2023-03-28 电子科技大学 一种异步先入先出的数据缓存控制器
GB2597054A (en) * 2020-07-02 2022-01-19 Technologies Oy Nokia Method and apparatus configured to provide clock domain separation
CN112084730B (zh) * 2020-09-11 2024-04-05 昇显微电子(苏州)股份有限公司 一种改善Asynchronous FIFO支持非2的幂次深度方法
CN112286489A (zh) * 2020-10-21 2021-01-29 深圳市紫光同创电子有限公司 Fifo存储器及fifo存储器的处理方法
CN112416823B (zh) * 2020-11-15 2024-05-03 珠海一微半导体股份有限公司 一种突发模式下的传感器数据读写控制方法、系统及芯片
CN118567605B (zh) * 2024-08-01 2024-10-15 上海韬润半导体有限公司 一种同源pll时钟下降低fifo延时的实现方法及系统

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US5473756A (en) 1992-12-30 1995-12-05 Intel Corporation FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers
KR0123239B1 (ko) 1994-07-06 1997-11-26 김주용 선입선출방식(fifo) 메모리
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JP3998314B2 (ja) 1998-01-21 2007-10-24 沖電気工業株式会社 先入れ先出し記憶装置
US6434642B1 (en) 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US6553448B1 (en) * 2001-03-01 2003-04-22 3Com Corporation Method for unit distance encoding of asynchronous pointers for non-power-of-two sized buffers
US7127536B2 (en) 2002-09-30 2006-10-24 Hewlett-Packard Development Company, L.P. Source-synchronous receiver having a predetermined data receive time
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US6794997B2 (en) * 2003-02-18 2004-09-21 Sun Microsystems, Inc. Extending non-volatile memory endurance using data encoding
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US8847002B2 (en) * 2011-05-19 2014-09-30 Kimberly-Clark Worldwide, Inc. Absorbent article containing apertures arranged in registration with an embossed wave pattern
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Also Published As

Publication number Publication date
DE602008004500D1 (en) 2011-02-24
EP2149083A1 (de) 2010-02-03
US8612651B2 (en) 2013-12-17
EP2149083B1 (de) 2011-01-12
CN101681249A (zh) 2010-03-24
WO2008142610A1 (en) 2008-11-27
CN101681249B (zh) 2012-12-05
US20100306426A1 (en) 2010-12-02

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