ATE495489T1 - Fifo-puffer - Google Patents
Fifo-pufferInfo
- Publication number
- ATE495489T1 ATE495489T1 AT08776408T AT08776408T ATE495489T1 AT E495489 T1 ATE495489 T1 AT E495489T1 AT 08776408 T AT08776408 T AT 08776408T AT 08776408 T AT08776408 T AT 08776408T AT E495489 T1 ATE495489 T1 AT E495489T1
- Authority
- AT
- Austria
- Prior art keywords
- circuit
- address
- write pointer
- read
- clock
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
- Air Bags (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07108299 | 2007-05-16 | ||
PCT/IB2008/051894 WO2008142610A1 (en) | 2007-05-16 | 2008-05-14 | Fifo buffer |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE495489T1 true ATE495489T1 (de) | 2011-01-15 |
Family
ID=39735570
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT08776408T ATE495489T1 (de) | 2007-05-16 | 2008-05-14 | Fifo-puffer |
Country Status (6)
Country | Link |
---|---|
US (1) | US8612651B2 (de) |
EP (1) | EP2149083B1 (de) |
CN (1) | CN101681249B (de) |
AT (1) | ATE495489T1 (de) |
DE (1) | DE602008004500D1 (de) |
WO (1) | WO2008142610A1 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BRPI1007631A2 (pt) * | 2009-05-05 | 2016-02-23 | Konink Philipis Electronics N V | método para proteger comunicações entre um dispositivo de recursos restritos e um dispositivo de recepção de acordo com um protocolo sem fio, dispositivo de recursos restritos e dispositivo sem bateria |
US8332596B2 (en) * | 2009-06-12 | 2012-12-11 | Cray Inc. | Multiple error management in a multiprocessor computer system |
US8417982B1 (en) * | 2009-08-11 | 2013-04-09 | Marvell Israel (M.I.S.L.) Ltd. | Dual clock first-in first-out (FIFO) memory system |
TWI504154B (zh) * | 2010-07-30 | 2015-10-11 | Realtek Semiconductor Corp | 多相位時脈切換裝置與其方法 |
CN102654827B (zh) * | 2011-03-02 | 2014-05-28 | 安凯(广州)微电子技术有限公司 | 一种先进先出缓冲器及缓存数据的方法 |
CN102880442B (zh) * | 2011-07-13 | 2015-05-27 | 瑞昱半导体股份有限公司 | 用于时钟树转换处的先入先出(fifo)装置与方法 |
CN102495713A (zh) * | 2011-12-09 | 2012-06-13 | 盛科网络(苏州)有限公司 | 实现任意深度异步fifo的方法及系统 |
US9911470B2 (en) | 2011-12-15 | 2018-03-06 | Nvidia Corporation | Fast-bypass memory circuit |
US8924612B2 (en) * | 2012-04-04 | 2014-12-30 | Arm Limited | Apparatus and method for providing a bidirectional communications link between a master device and a slave device |
CN102799410B (zh) * | 2012-06-19 | 2015-03-04 | 东南大学 | 基于李氏制约竞争计数编码的异步fifo地址转换电路 |
CN103632712A (zh) | 2012-08-27 | 2014-03-12 | 辉达公司 | 存储单元和存储器 |
US9685207B2 (en) | 2012-12-04 | 2017-06-20 | Nvidia Corporation | Sequential access memory with master-slave latch pairs and method of operating |
US9281817B2 (en) * | 2012-12-31 | 2016-03-08 | Nvidia Corporation | Power conservation using gray-coded address sequencing |
US10141930B2 (en) | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
US9672008B2 (en) * | 2014-11-24 | 2017-06-06 | Nvidia Corporation | Pausible bisynchronous FIFO |
US9509640B2 (en) * | 2014-12-05 | 2016-11-29 | Xilinx, Inc. | Latency control in a transmitter/receiver buffer |
US10775836B2 (en) * | 2015-06-16 | 2020-09-15 | Synopsys, Inc. | Method for cycle accurate data transfer in a skewed synchronous clock domain |
US10254967B2 (en) | 2016-01-13 | 2019-04-09 | Sandisk Technologies Llc | Data path control for non-volatile memory |
US10528286B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Interface for non-volatile memory |
US10528255B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Interface for non-volatile memory |
US10528267B2 (en) | 2016-11-11 | 2020-01-07 | Sandisk Technologies Llc | Command queue for storage operations |
US10114589B2 (en) | 2016-11-16 | 2018-10-30 | Sandisk Technologies Llc | Command control for multi-core non-volatile memory |
KR102342547B1 (ko) * | 2017-07-12 | 2021-12-23 | 삼성전자주식회사 | 버퍼 컨트롤러, 메모리 장치 및 집적회로 장치 |
US11010293B1 (en) * | 2018-01-23 | 2021-05-18 | Marvell Israel (M.I.S.L) Ltd. | Register-based asynchronous FIFO with asymmetric size |
US11436166B2 (en) * | 2019-02-05 | 2022-09-06 | Arm Limited | Data processing systems |
US11461030B2 (en) * | 2019-07-15 | 2022-10-04 | Micron Technology, Inc. | Transferring data between clock domains using pulses across a queue |
CN111367495B (zh) * | 2020-03-06 | 2023-03-28 | 电子科技大学 | 一种异步先入先出的数据缓存控制器 |
GB2597054A (en) * | 2020-07-02 | 2022-01-19 | Technologies Oy Nokia | Method and apparatus configured to provide clock domain separation |
CN112084730B (zh) * | 2020-09-11 | 2024-04-05 | 昇显微电子(苏州)股份有限公司 | 一种改善Asynchronous FIFO支持非2的幂次深度方法 |
CN112286489A (zh) * | 2020-10-21 | 2021-01-29 | 深圳市紫光同创电子有限公司 | Fifo存储器及fifo存储器的处理方法 |
CN112416823B (zh) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种突发模式下的传感器数据读写控制方法、系统及芯片 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3421147A (en) * | 1965-05-07 | 1969-01-07 | Bell Telephone Labor Inc | Buffer arrangement |
US4834733A (en) * | 1987-11-12 | 1989-05-30 | Kimberly-Clark Corporation | Fluid activated mechanical absorbency gauge |
US5426756A (en) * | 1992-08-11 | 1995-06-20 | S3, Incorporated | Memory controller and method determining empty/full status of a FIFO memory using gray code counters |
US5473756A (en) * | 1992-12-30 | 1995-12-05 | Intel Corporation | FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers |
KR0123239B1 (ko) * | 1994-07-06 | 1997-11-26 | 김주용 | 선입선출방식(fifo) 메모리 |
EP0760501B1 (de) * | 1995-09-04 | 2002-02-20 | Hewlett-Packard Company, A Delaware Corporation | Dataverarbeitungssystem mit ringförmiger Warteschlange in einem Seitenspeicher |
US5699530A (en) * | 1995-10-03 | 1997-12-16 | Intel Corporation | Circular RAM-based first-in/first-out buffer employing interleaved storage locations and cross pointers |
US6101329A (en) * | 1997-02-18 | 2000-08-08 | Lsi Logic Corporation | System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data |
US6075931A (en) * | 1997-06-25 | 2000-06-13 | Sun Microsystems, Inc. | Method for efficient implementation of multi-ported logic FIFO structures in a processor |
JP3998314B2 (ja) * | 1998-01-21 | 2007-10-24 | 沖電気工業株式会社 | 先入れ先出し記憶装置 |
US6434642B1 (en) * | 1999-10-07 | 2002-08-13 | Xilinx, Inc. | FIFO memory system and method with improved determination of full and empty conditions and amount of data stored |
US6553448B1 (en) * | 2001-03-01 | 2003-04-22 | 3Com Corporation | Method for unit distance encoding of asynchronous pointers for non-power-of-two sized buffers |
US7127536B2 (en) * | 2002-09-30 | 2006-10-24 | Hewlett-Packard Development Company, L.P. | Source-synchronous receiver having a predetermined data receive time |
FR2849228A1 (fr) * | 2002-12-23 | 2004-06-25 | St Microelectronics Sa | Dispositif de transfert de donnees entre deux sous-systemes asynchrones disposant d'une memoire tampon |
US6794997B2 (en) * | 2003-02-18 | 2004-09-21 | Sun Microsystems, Inc. | Extending non-volatile memory endurance using data encoding |
US7293149B2 (en) * | 2003-05-30 | 2007-11-06 | Sun Microsystems Inc. | Method and apparatus for determining a status of an asynchronous memory |
US7519788B2 (en) * | 2004-06-04 | 2009-04-14 | Micron Technology, Inc. | System and method for an asynchronous data buffer having buffer write and read pointers |
JP4417807B2 (ja) * | 2004-08-25 | 2010-02-17 | 株式会社東芝 | エラスティックバッファ |
US9044356B2 (en) * | 2011-05-19 | 2015-06-02 | Kimberly-Clark Worldwide, Inc. | Absorbent article having enhanced leakage protection |
US8847002B2 (en) * | 2011-05-19 | 2014-09-30 | Kimberly-Clark Worldwide, Inc. | Absorbent article containing apertures arranged in registration with an embossed wave pattern |
US9220646B2 (en) * | 2012-03-30 | 2015-12-29 | Kimberly-Clark Worldwide, Inc. | Absorbent articles with improved stain decolorization |
-
2008
- 2008-05-14 EP EP08776408A patent/EP2149083B1/de not_active Not-in-force
- 2008-05-14 CN CN2008800160770A patent/CN101681249B/zh not_active Expired - Fee Related
- 2008-05-14 AT AT08776408T patent/ATE495489T1/de not_active IP Right Cessation
- 2008-05-14 WO PCT/IB2008/051894 patent/WO2008142610A1/en active Application Filing
- 2008-05-14 DE DE602008004500T patent/DE602008004500D1/de active Active
- 2008-05-14 US US12/599,062 patent/US8612651B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8612651B2 (en) | 2013-12-17 |
CN101681249B (zh) | 2012-12-05 |
DE602008004500D1 (en) | 2011-02-24 |
CN101681249A (zh) | 2010-03-24 |
US20100306426A1 (en) | 2010-12-02 |
EP2149083A1 (de) | 2010-02-03 |
EP2149083B1 (de) | 2011-01-12 |
WO2008142610A1 (en) | 2008-11-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE495489T1 (de) | Fifo-puffer | |
US9275704B2 (en) | Method and apparatus for asynchronous FIFO circuit | |
TW200739418A (en) | Command decoder for microcontroller based flash memory digital controller system | |
ES2804604T3 (es) | Técnicas de ahorro de energía para sistemas de memoria | |
US7177230B1 (en) | Memory controller and memory system | |
JP6265944B2 (ja) | 電圧ドメインクロッシングのためのデータ記憶 | |
WO2008130418A3 (en) | Calibration of read/write memory access via advanced memory buffer | |
TW200623125A (en) | Clock signal generation apparatus for use in semiconductor memory device and its method | |
US9142268B2 (en) | Dual-voltage domain memory buffers, and related systems and methods | |
KR20180057028A (ko) | 데이터 반전 회로 | |
JP2013175261A (ja) | コマンドデコーダ | |
US8412883B2 (en) | Memory controller and associated control method | |
KR102570454B1 (ko) | 반도체 메모리 장치 및 그의 동작 방법 | |
KR20080016681A (ko) | 단방향성 풀 듀플렉스 인터페이스를 갖는 메모리를 위한포스트된 기록 버퍼용 방법, 장치, 시스템 및 저장 매체 | |
TW200627466A (en) | An architecture for reading and writing an external memory | |
DE60236913D1 (de) | Verfahren und Schaltung zur Initialisierung eines Laufzeitausgleichpuffers in einem taktweitergeleiteten System | |
KR20130119170A (ko) | 파이프 레지스터 회로 및 이를 포함하는 반도체 메모리 장치 | |
US20180174623A1 (en) | Apparatus and method for transferring data between different voltage-clock domains using multiple write-side multiplexers | |
US20190042108A1 (en) | Nonvolatile memory store suppresion | |
JP2006172672A (ja) | Fifoメモリ | |
TW200745860A (en) | Memory access device | |
TW200723292A (en) | Semiconductor memory device | |
US9251887B2 (en) | Static random access memory system and operation method thereof | |
TW201721444A (zh) | 高速資料介面主機端控制器 | |
US8185671B2 (en) | Technique for increasing control and status signal density in a fixed register address space |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |