CN112084730B - 一种改善Asynchronous FIFO支持非2的幂次深度方法 - Google Patents
一种改善Asynchronous FIFO支持非2的幂次深度方法 Download PDFInfo
- Publication number
- CN112084730B CN112084730B CN202010950156.1A CN202010950156A CN112084730B CN 112084730 B CN112084730 B CN 112084730B CN 202010950156 A CN202010950156 A CN 202010950156A CN 112084730 B CN112084730 B CN 112084730B
- Authority
- CN
- China
- Prior art keywords
- full
- logic circuit
- depth
- condition
- gray code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 13
- 238000006073 displacement reaction Methods 0.000 claims abstract description 18
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 229910002056 binary alloy Inorganic materials 0.000 claims description 3
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000009795 derivation Methods 0.000 claims description 2
- 238000013461 design Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Image Generation (AREA)
- Communication Control (AREA)
Abstract
Description
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010950156.1A CN112084730B (zh) | 2020-09-11 | 2020-09-11 | 一种改善Asynchronous FIFO支持非2的幂次深度方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010950156.1A CN112084730B (zh) | 2020-09-11 | 2020-09-11 | 一种改善Asynchronous FIFO支持非2的幂次深度方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112084730A CN112084730A (zh) | 2020-12-15 |
CN112084730B true CN112084730B (zh) | 2024-04-05 |
Family
ID=73737356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010950156.1A Active CN112084730B (zh) | 2020-09-11 | 2020-09-11 | 一种改善Asynchronous FIFO支持非2的幂次深度方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112084730B (zh) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4672307A (en) * | 1985-12-20 | 1987-06-09 | University Of Southern California | Simplified delay testing for LSI circuit faults |
JP2006005954A (ja) * | 2005-07-19 | 2006-01-05 | Sharp Corp | グレーコードカウンタ |
CN101373424A (zh) * | 2008-09-19 | 2009-02-25 | 北京中星微电子有限公司 | 一种异步先进先出存储器的数据读写方法、装置及系统 |
US7518535B1 (en) * | 2007-12-12 | 2009-04-14 | International Business Machines Corporation | Generating a Gray code sequence for any even length using an intermediate binary sequence |
CN101681249A (zh) * | 2007-05-16 | 2010-03-24 | Nxp股份有限公司 | 先进先出缓冲器 |
CN205375448U (zh) * | 2014-10-07 | 2016-07-06 | 意法半导体股份有限公司 | 双同步电子设备和fifo存储器电路 |
CN110888622A (zh) * | 2018-09-11 | 2020-03-17 | 上海肇观电子科技有限公司 | 实现任意深度异步fifo的方法及装置、设备、介质 |
-
2020
- 2020-09-11 CN CN202010950156.1A patent/CN112084730B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4672307A (en) * | 1985-12-20 | 1987-06-09 | University Of Southern California | Simplified delay testing for LSI circuit faults |
JP2006005954A (ja) * | 2005-07-19 | 2006-01-05 | Sharp Corp | グレーコードカウンタ |
CN101681249A (zh) * | 2007-05-16 | 2010-03-24 | Nxp股份有限公司 | 先进先出缓冲器 |
US7518535B1 (en) * | 2007-12-12 | 2009-04-14 | International Business Machines Corporation | Generating a Gray code sequence for any even length using an intermediate binary sequence |
CN101373424A (zh) * | 2008-09-19 | 2009-02-25 | 北京中星微电子有限公司 | 一种异步先进先出存储器的数据读写方法、装置及系统 |
CN205375448U (zh) * | 2014-10-07 | 2016-07-06 | 意法半导体股份有限公司 | 双同步电子设备和fifo存储器电路 |
CN110888622A (zh) * | 2018-09-11 | 2020-03-17 | 上海肇观电子科技有限公司 | 实现任意深度异步fifo的方法及装置、设备、介质 |
Non-Patent Citations (1)
Title |
---|
高速模数转换器中格雷码与二进制编码对比;刘海涛;王志功;孟桥;唐凯;;东南大学学报(自然科学版);20100520(第03期);全文 * |
Also Published As
Publication number | Publication date |
---|---|
CN112084730A (zh) | 2020-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111367495B (zh) | 一种异步先入先出的数据缓存控制器 | |
CN101681249B (zh) | 先进先出缓冲器 | |
KR100819061B1 (ko) | 쓰기 전력 계산 및 데이터 반전 기능을 통한 상 변화메모리에서의 데이터 쓰기 장치 및 방법 | |
US7571297B2 (en) | Data invalid signal for non-deterministic latency in a memory system | |
CN107454203A (zh) | 在分布式系统中生成唯一id的方法 | |
CN101692651A (zh) | 一种哈希查找表的方法和装置 | |
US6845414B2 (en) | Apparatus and method of asynchronous FIFO control | |
CN101373424A (zh) | 一种异步先进先出存储器的数据读写方法、装置及系统 | |
CN100549938C (zh) | Fifo控制电路及控制方法 | |
CN112181306A (zh) | 一种号段模式下生成分布式id的方法 | |
WO2020010742A1 (zh) | 单线传输方法、芯片以及通信系统 | |
EP2219114A1 (en) | Method and apparatus for allocating storage addresses | |
CN112084730B (zh) | 一种改善Asynchronous FIFO支持非2的幂次深度方法 | |
CN101227689B (zh) | 信息上报方法及装置 | |
CN115361012A (zh) | 一种低功耗异步先入先出缓存器电路及芯片 | |
CN109710309A (zh) | 减少存储体冲突的方法 | |
CN114201276A (zh) | 一种基于fifo中断管理的方法 | |
CN101493759B (zh) | 一种任意容量异步先入先出存储器的地址控制方法 | |
CN111143079B (zh) | 一种多读多写无锁队列实现方法 | |
CN115221082B (zh) | 一种数据缓存方法、装置及存储介质 | |
CN1859047B (zh) | 帧同步处理装置及方法 | |
CN112163184B (zh) | 一种实现fft的装置及方法 | |
CN108462655B (zh) | Fc链路弹性缓冲区电路 | |
CN108319804B (zh) | 低资源调用的8192点基2 dit asic设计方法 | |
CN107562553B (zh) | 数据中心管理方法和设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: Room 1905, building 4, No.209, Zhuyuan Road, Suzhou hi tech Zone, Suzhou, Jiangsu 215000 Applicant after: Sunrise Microelectronics (Suzhou) Co.,Ltd. Address before: Room 1905, building 4, No.209, Zhuyuan Road, Suzhou hi tech Zone, Suzhou, Jiangsu 215000 Applicant before: Sheng Microelectronics (Suzhou) Co.,Ltd. |
|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A method to improve asynchronous FIFO support for non 2 power depth Granted publication date: 20240405 Pledgee: Bank of China Limited Suzhou high tech Industrial Development Zone sub branch Pledgor: Sunrise Microelectronics (Suzhou) Co.,Ltd. Registration number: Y2024980022096 |