ATE467182T1 - Patrouillen-snooping zur kandidatenidentifikation für die cache-ausräumung auf höherer ebene - Google Patents

Patrouillen-snooping zur kandidatenidentifikation für die cache-ausräumung auf höherer ebene

Info

Publication number
ATE467182T1
ATE467182T1 AT07703995T AT07703995T ATE467182T1 AT E467182 T1 ATE467182 T1 AT E467182T1 AT 07703995 T AT07703995 T AT 07703995T AT 07703995 T AT07703995 T AT 07703995T AT E467182 T1 ATE467182 T1 AT E467182T1
Authority
AT
Austria
Prior art keywords
level cache
higher level
patrol
cache
snooping
Prior art date
Application number
AT07703995T
Other languages
German (de)
English (en)
Inventor
John Borkenhagen
Brian Vanderpool
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE467182T1 publication Critical patent/ATE467182T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT07703995T 2006-01-19 2007-01-18 Patrouillen-snooping zur kandidatenidentifikation für die cache-ausräumung auf höherer ebene ATE467182T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/335,765 US7577793B2 (en) 2006-01-19 2006-01-19 Patrol snooping for higher level cache eviction candidate identification
PCT/EP2007/050503 WO2007082917A2 (en) 2006-01-19 2007-01-18 Patrol snooping for higher level cache eviction candidate identification

Publications (1)

Publication Number Publication Date
ATE467182T1 true ATE467182T1 (de) 2010-05-15

Family

ID=37955186

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07703995T ATE467182T1 (de) 2006-01-19 2007-01-18 Patrouillen-snooping zur kandidatenidentifikation für die cache-ausräumung auf höherer ebene

Country Status (8)

Country Link
US (1) US7577793B2 (https=)
EP (1) EP1977322B1 (https=)
JP (1) JP4563486B2 (https=)
CN (1) CN101361049B (https=)
AT (1) ATE467182T1 (https=)
DE (1) DE602007006277D1 (https=)
TW (1) TWI417723B (https=)
WO (1) WO2007082917A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7624234B2 (en) * 2006-08-31 2009-11-24 Hewlett-Packard Development Company, L.P. Directory caches, and methods for operation thereof
JP4920378B2 (ja) * 2006-11-17 2012-04-18 株式会社東芝 情報処理装置およびデータ検索方法
US7457920B1 (en) 2008-01-26 2008-11-25 International Business Machines Corporation Method and system for cache eviction
US8271735B2 (en) * 2009-01-13 2012-09-18 Oracle America, Inc. Cache-coherency protocol with held state
JP2011028736A (ja) * 2009-07-02 2011-02-10 Fujitsu Ltd キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法
US8566531B2 (en) * 2009-08-21 2013-10-22 Google Inc. System and method of selectively caching information based on the interarrival time of requests for the same information
AU2010201718B2 (en) * 2010-04-29 2012-08-23 Canon Kabushiki Kaisha Method, system and apparatus for identifying a cache line
US8769209B2 (en) * 2010-12-20 2014-07-01 Intel Corporation Method and apparatus for achieving non-inclusive cache performance with inclusive caches
US9804971B2 (en) * 2012-01-17 2017-10-31 International Business Machines Corporation Cache management of track removal in a cache for storage
WO2016055828A1 (en) * 2014-10-08 2016-04-14 Via Alliance Semiconductor Co., Ltd. Cache system with primary cache and overflow fifo cache
US10255190B2 (en) * 2015-12-17 2019-04-09 Advanced Micro Devices, Inc. Hybrid cache
JP6708019B2 (ja) 2016-06-29 2020-06-10 富士通株式会社 演算処理装置、情報処理装置および演算処理装置の制御方法
CN109074320B (zh) * 2017-03-08 2023-11-17 华为技术有限公司 一种缓存替换方法,装置和系统
US20190012259A1 (en) * 2017-07-06 2019-01-10 Futurewei Technologies, Inc. Lba eviction in pcm media
US10915461B2 (en) * 2019-03-05 2021-02-09 International Business Machines Corporation Multilevel cache eviction management
US10997074B2 (en) 2019-04-30 2021-05-04 Hewlett Packard Enterprise Development Lp Management of coherency directory cache entry ejection

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5373927A (en) * 1976-11-10 1978-06-30 Fujitsu Ltd Replacing system of intermediate buffer memory
JPH01199251A (ja) * 1988-02-04 1989-08-10 Fujitsu Ltd キャッシュメモリアクセス制御方式
JPH02188847A (ja) * 1989-01-18 1990-07-24 Agency Of Ind Science & Technol 階層キャッシュメモリにおけるデータ交換方式
JPH05216765A (ja) * 1992-02-06 1993-08-27 Hitachi Ltd 階層バッファ記憶装置
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
US5850534A (en) * 1995-06-05 1998-12-15 Advanced Micro Devices, Inc. Method and apparatus for reducing cache snooping overhead in a multilevel cache system
US5829038A (en) * 1996-06-20 1998-10-27 Intel Corporation Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure
JPH10105463A (ja) * 1996-09-27 1998-04-24 Mitsubishi Electric Corp キャッシュシステム及びリプレース判定方法
JPH11102320A (ja) * 1997-09-29 1999-04-13 Mitsubishi Electric Corp キャッシュシステム
US6023747A (en) * 1997-12-17 2000-02-08 International Business Machines Corporation Method and system for handling conflicts between cache operation requests in a data processing system
US6343344B1 (en) * 1999-08-04 2002-01-29 International Business Machines Corporation System bus directory snooping mechanism for read/castout (RCO) address transaction
US6901450B1 (en) * 2000-09-22 2005-05-31 Hitachi, Ltd. Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors
US6725337B1 (en) * 2001-05-16 2004-04-20 Advanced Micro Devices, Inc. Method and system for speculatively invalidating lines in a cache
US7024545B1 (en) * 2001-07-24 2006-04-04 Advanced Micro Devices, Inc. Hybrid branch prediction device with two levels of branch prediction cache
TWI246658B (en) * 2003-04-25 2006-01-01 Ip First Llc Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US7143246B2 (en) * 2004-01-16 2006-11-28 International Business Machines Corporation Method for supporting improved burst transfers on a coherent bus
US20070186045A1 (en) * 2004-07-23 2007-08-09 Shannon Christopher J Cache eviction technique for inclusive cache systems
US20060212654A1 (en) * 2005-03-18 2006-09-21 Vinod Balakrishnan Method and apparatus for intelligent instruction caching using application characteristics
US20070073974A1 (en) * 2005-09-29 2007-03-29 International Business Machines Corporation Eviction algorithm for inclusive lower level cache based upon state of higher level cache

Also Published As

Publication number Publication date
WO2007082917A2 (en) 2007-07-26
CN101361049B (zh) 2011-12-28
US20070168617A1 (en) 2007-07-19
WO2007082917A3 (en) 2007-10-04
TW200805061A (en) 2008-01-16
CN101361049A (zh) 2009-02-04
DE602007006277D1 (de) 2010-06-17
JP2009524137A (ja) 2009-06-25
EP1977322B1 (en) 2010-05-05
JP4563486B2 (ja) 2010-10-13
EP1977322A2 (en) 2008-10-08
TWI417723B (zh) 2013-12-01
US7577793B2 (en) 2009-08-18

Similar Documents

Publication Publication Date Title
ATE467182T1 (de) Patrouillen-snooping zur kandidatenidentifikation für die cache-ausräumung auf höherer ebene
GB201210115D0 (en) Shared cache memory control
GB201303300D0 (en) Data Processing
GB2485083A (en) Checkpointing in speculative versioning caches
SI2229620T1 (sl) Naprava za ekstrahiranje atributov v predpomnilniku in ukaz zanjo
Guintivano et al. Role of epigenetic factors in the development of mental illness throughout life
GB2487697A (en) Methods and systems for identifying, assessing and clearing conflicts of interest
GB2433807A (en) Caching support for direct memory access address translation
JP2009524137A5 (https=)
TW200951715A (en) Memory system
GB201211273D0 (en) Multilevel cache system
TW200707190A (en) Partial page scheme for memory technologies
ATE412779T1 (de) Benutzung von intronischen rna sequenzen zur quantifizierung der genexpression
WO2008155805A1 (ja) キャッシュメモリ装置、演算処理装置及びその制御方法
GB2455457A (en) Data cache virtual hint way prediction, and applications thereof
ATE522867T1 (de) Verfahren zur synchronisierung von datencaches
BR112012009262A2 (pt) ''método para inibir a proliferação de células de câncer positivo para ar em um indivíduo diagnosticado com,ou qual se suspeita que tenha cânce positivo para ar e método para identificar se um indivíduo é um candidato para tratamento com uma composiçâo
DE602007007566D1 (de) Verschleierung von Speicherzugriffsmustern
GB2478507A (en) System and method for providing content to a mobile device
GB2463409A (en) Preventing writeback race in multiple core processors
IL169265A0 (en) Page descriptors for prefetching and memory management
GB201210995D0 (en) Methods and systems for managing cache memories
WO2007084484A3 (en) System and method of multi-core cache coherency
TW200710674A (en) Processor, data processing system, and method for initializing a memory block
TW200627155A (en) Pre-fetch technology by read merge mechanism

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties