SI2229620T1 - Naprava za ekstrahiranje atributov v predpomnilniku in ukaz zanjo - Google Patents

Naprava za ekstrahiranje atributov v predpomnilniku in ukaz zanjo

Info

Publication number
SI2229620T1
SI2229620T1 SI200930067T SI200930067T SI2229620T1 SI 2229620 T1 SI2229620 T1 SI 2229620T1 SI 200930067 T SI200930067 T SI 200930067T SI 200930067 T SI200930067 T SI 200930067T SI 2229620 T1 SI2229620 T1 SI 2229620T1
Authority
SI
Slovenia
Prior art keywords
cache
instruction
cache attribute
target
extract cache
Prior art date
Application number
SI200930067T
Other languages
English (en)
Inventor
Dan Greiner
Timothy Slegel
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SI2229620T1 publication Critical patent/SI2229620T1/sl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
SI200930067T 2008-01-11 2009-01-07 Naprava za ekstrahiranje atributov v predpomnilniku in ukaz zanjo SI2229620T1 (sl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/972,675 US7870339B2 (en) 2008-01-11 2008-01-11 Extract cache attribute facility and instruction therefore
EP09700229A EP2229620B1 (en) 2008-01-11 2009-01-07 Extract cache attribute facility and instruction therefore
PCT/EP2009/050107 WO2009087160A1 (en) 2008-01-11 2009-01-07 Extract cache attribute facility and instruction therefore

Publications (1)

Publication Number Publication Date
SI2229620T1 true SI2229620T1 (sl) 2011-10-28

Family

ID=40513439

Family Applications (1)

Application Number Title Priority Date Filing Date
SI200930067T SI2229620T1 (sl) 2008-01-11 2009-01-07 Naprava za ekstrahiranje atributov v predpomnilniku in ukaz zanjo

Country Status (16)

Country Link
US (3) US7870339B2 (sl)
EP (1) EP2229620B1 (sl)
JP (1) JP5052678B2 (sl)
KR (1) KR101231562B1 (sl)
CN (1) CN101911013B (sl)
AT (1) ATE516538T1 (sl)
BR (1) BRPI0906424B1 (sl)
CA (1) CA2701093C (sl)
CY (1) CY1112472T1 (sl)
DK (1) DK2229620T3 (sl)
ES (1) ES2368682T3 (sl)
IL (1) IL206848A (sl)
PL (1) PL2229620T3 (sl)
PT (1) PT2229620E (sl)
SI (1) SI2229620T1 (sl)
WO (1) WO2009087160A1 (sl)

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US9280480B2 (en) 2008-01-11 2016-03-08 International Business Machines Corporation Extract target cache attribute facility and instruction therefor
US8151076B2 (en) * 2008-04-04 2012-04-03 Cisco Technology, Inc. Mapping memory segments in a translation lookaside buffer
US9268566B2 (en) 2012-03-15 2016-02-23 International Business Machines Corporation Character data match determination by loading registers at most up to memory block boundary and comparing
US9280347B2 (en) 2012-03-15 2016-03-08 International Business Machines Corporation Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
US9715383B2 (en) 2012-03-15 2017-07-25 International Business Machines Corporation Vector find element equal instruction
US9454366B2 (en) 2012-03-15 2016-09-27 International Business Machines Corporation Copying character data having a termination character from one memory location to another
US9710266B2 (en) 2012-03-15 2017-07-18 International Business Machines Corporation Instruction to compute the distance to a specified memory boundary
US9459864B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Vector string range compare
US9588762B2 (en) 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
US9459867B2 (en) * 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a specified memory boundary indicated by the instruction
US9454367B2 (en) * 2012-03-15 2016-09-27 International Business Machines Corporation Finding the length of a set of character data having a termination character
US9459868B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a dynamically determined memory boundary
US10620957B2 (en) * 2015-10-22 2020-04-14 Texas Instruments Incorporated Method for forming constant extensions in the same execute packet in a VLIW processor
US10713048B2 (en) * 2017-01-19 2020-07-14 International Business Machines Corporation Conditional branch to an indirectly specified location
CN109408429B (zh) * 2018-11-01 2020-10-16 苏州浪潮智能科技有限公司 一种低速接口的缓存方法与装置
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
US20220179787A1 (en) 2019-03-15 2022-06-09 Intel Corporation Systems and methods for improving cache efficiency and utilization
JP7408671B2 (ja) 2019-03-15 2024-01-05 インテル コーポレイション シストリックアレイに対するブロックスパース演算のためのアーキテクチャ
CN117093510B (zh) * 2023-05-30 2024-04-09 中国人民解放军军事科学院国防科技创新研究院 大小端通用的缓存行高效索引方法

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Also Published As

Publication number Publication date
CN101911013A (zh) 2010-12-08
BRPI0906424A2 (pt) 2016-10-11
EP2229620A1 (en) 2010-09-22
JP5052678B2 (ja) 2012-10-17
CN101911013B (zh) 2013-07-31
IL206848A (en) 2014-03-31
CY1112472T1 (el) 2015-12-09
PT2229620E (pt) 2011-10-06
US20110131382A1 (en) 2011-06-02
DK2229620T3 (da) 2011-09-05
US8131934B2 (en) 2012-03-06
JP2011509475A (ja) 2011-03-24
KR20100106444A (ko) 2010-10-01
US7870339B2 (en) 2011-01-11
KR101231562B1 (ko) 2013-02-12
ES2368682T3 (es) 2011-11-21
US8516195B2 (en) 2013-08-20
EP2229620B1 (en) 2011-07-13
ATE516538T1 (de) 2011-07-15
CA2701093C (en) 2016-10-11
PL2229620T3 (pl) 2011-12-30
IL206848A0 (en) 2010-12-30
WO2009087160A1 (en) 2009-07-16
US20120137073A1 (en) 2012-05-31
US20090182942A1 (en) 2009-07-16
BRPI0906424B1 (pt) 2020-10-20
CA2701093A1 (en) 2009-07-16

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