ATE465511T1 - Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode - Google Patents

Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode

Info

Publication number
ATE465511T1
ATE465511T1 AT04786450T AT04786450T ATE465511T1 AT E465511 T1 ATE465511 T1 AT E465511T1 AT 04786450 T AT04786450 T AT 04786450T AT 04786450 T AT04786450 T AT 04786450T AT E465511 T1 ATE465511 T1 AT E465511T1
Authority
AT
Austria
Prior art keywords
transistor
metal silicide
forming
gate electrode
trench
Prior art date
Application number
AT04786450T
Other languages
English (en)
Inventor
Todd Abbot
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE465511T1 publication Critical patent/ATE465511T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
AT04786450T 2003-08-15 2004-08-04 Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode ATE465511T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/641,851 US7012024B2 (en) 2003-08-15 2003-08-15 Methods of forming a transistor with an integrated metal silicide gate electrode
PCT/US2004/025085 WO2005020282A2 (en) 2003-08-15 2004-08-04 Methods of forming a transistor with an integrated metal silicide gate electrode

Publications (1)

Publication Number Publication Date
ATE465511T1 true ATE465511T1 (de) 2010-05-15

Family

ID=34136456

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04786450T ATE465511T1 (de) 2003-08-15 2004-08-04 Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode

Country Status (9)

Country Link
US (2) US7012024B2 (de)
EP (1) EP1656696B1 (de)
JP (1) JP4826914B2 (de)
KR (1) KR100669627B1 (de)
CN (1) CN100421226C (de)
AT (1) ATE465511T1 (de)
DE (1) DE602004026737D1 (de)
TW (1) TWI245418B (de)
WO (1) WO2005020282A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7012024B2 (en) 2003-08-15 2006-03-14 Micron Technology, Inc. Methods of forming a transistor with an integrated metal silicide gate electrode
KR100555541B1 (ko) * 2003-12-23 2006-03-03 삼성전자주식회사 코발트 실리사이드막 형성방법 및 그 형성방법을 이용한반도체 장치의 제조방법
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) * 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7888721B2 (en) * 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) * 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7875959B2 (en) * 2005-08-31 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having selective silicide-induced stress and a method of producing same
US7867845B2 (en) * 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures
US7678607B2 (en) 2007-02-05 2010-03-16 Intermolecular, Inc. Methods for forming resistive switching memory elements
US7972897B2 (en) 2007-02-05 2011-07-05 Intermolecular, Inc. Methods for forming resistive switching memory elements
US7704789B2 (en) 2007-02-05 2010-04-27 Intermolecular, Inc. Methods for forming resistive switching memory elements
US8097878B2 (en) 2007-03-05 2012-01-17 Intermolecular, Inc. Nonvolatile memory elements with metal-deficient resistive-switching metal oxides
WO2008109199A1 (en) * 2007-03-05 2008-09-12 Intermolecular, Inc. Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US7629198B2 (en) 2007-03-05 2009-12-08 Intermolecular, Inc. Methods for forming nonvolatile memory elements with resistive-switching metal oxides
JP5422552B2 (ja) 2007-05-09 2014-02-19 インターモレキュラー， インコーポレイテッド 抵抗性スイッチング不揮発性メモリ要素
KR101482814B1 (ko) 2007-07-25 2015-01-14 인터몰레큘러 인코퍼레이티드 다중상태 비휘발성 메모리 소자
US8294219B2 (en) 2007-07-25 2012-10-23 Intermolecular, Inc. Nonvolatile memory element including resistive switching metal oxide layers
US20090236675A1 (en) * 2008-03-21 2009-09-24 National Tsing Hua University Self-aligned field-effect transistor structure and manufacturing method thereof
KR101604054B1 (ko) * 2009-09-03 2016-03-16 삼성전자주식회사 반도체 소자 및 그 형성방법
US8030196B2 (en) * 2010-01-12 2011-10-04 Samsung Electronics Co., Ltd. Transistor formation using capping layer
CN113594237B (zh) * 2020-04-30 2023-09-26 长鑫存储技术有限公司 埋入式栅极制备方法和半导体器件制备方法
CN111739839B (zh) * 2020-06-23 2021-07-02 武汉新芯集成电路制造有限公司 自对准接触孔的制造方法、半导体器件的制造方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2652448B1 (fr) * 1989-09-28 1994-04-29 Commissariat Energie Atomique Procede de fabrication d'un circuit integre mis haute tension.
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5923971A (en) * 1996-10-22 1999-07-13 International Business Machines Corporation Reliable low resistance strap for trench storage DRAM cell using selective epitaxy
JPH11204791A (ja) * 1997-11-17 1999-07-30 Toshiba Corp 半導体装置及びその製造方法
US6291868B1 (en) * 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6177699B1 (en) * 1998-03-19 2001-01-23 Lsi Logic Corporation DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation
US6107154A (en) * 1998-05-12 2000-08-22 United Microelectronics Corp. Method of fabricating a semiconductor embedded dynamic random-access memory device
JP2002530864A (ja) * 1998-11-12 2002-09-17 インテル・コーポレーション 階段ソース／ドレイン接合部を有する電界効果トランジスタ構造
US6177333B1 (en) * 1999-01-14 2001-01-23 Micron Technology, Inc. Method for making a trench isolation for semiconductor devices
US6358788B1 (en) 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
US6372618B2 (en) * 2000-01-06 2002-04-16 Micron Technology, Inc. Methods of forming semiconductor structures
CN1173390C (zh) * 2000-10-30 2004-10-27 世界先进积体电路股份有限公司 具嵌入式栅极的金属氧化物半导体场效应晶体管的形成方法
US6388327B1 (en) * 2001-01-09 2002-05-14 International Business Machines Corporation Capping layer for improved silicide formation in narrow semiconductor structures
US6346477B1 (en) * 2001-01-09 2002-02-12 Research Foundation Of Suny - New York Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt
JP3992439B2 (ja) * 2001-01-16 2007-10-17 株式会社ルネサステクノロジ 半導体装置の製造方法
US6406962B1 (en) * 2001-01-17 2002-06-18 International Business Machines Corporation Vertical trench-formed dual-gate FET device structure and method for creation
US6458679B1 (en) * 2001-02-12 2002-10-01 Advanced Micro Devices, Inc. Method of making silicide stop layer in a damascene semiconductor structure
US6498062B2 (en) * 2001-04-27 2002-12-24 Micron Technology, Inc. DRAM access transistor
DE10126579C2 (de) * 2001-05-31 2003-12-11 Infineon Technologies Ag Verfahren zur Herstellung eines Gatestapels in ultrahochintegrierten Halbleiterspeichern
US20030011018A1 (en) * 2001-07-13 2003-01-16 Hurley Kelly T. Flash floating gate using epitaxial overgrowth
KR100418928B1 (ko) * 2001-10-24 2004-02-14 주식회사 하이닉스반도체 엠디엘 반도체 소자의 제조 방법
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US7132065B2 (en) 2003-02-12 2006-11-07 3M Innovative Properties Company Process for manufacturing polymeric optical film
KR100538806B1 (ko) * 2003-02-21 2005-12-26 주식회사 하이닉스반도체 에피택셜 ｃ49상의 티타늄실리사이드막을 갖는 반도체소자 및 그 제조 방법
US7012024B2 (en) 2003-08-15 2006-03-14 Micron Technology, Inc. Methods of forming a transistor with an integrated metal silicide gate electrode

Also Published As

Publication number Publication date
WO2005020282A2 (en) 2005-03-03
EP1656696B1 (de) 2010-04-21
JP2007503116A (ja) 2007-02-15
CN1868047A (zh) 2006-11-22
US7351659B2 (en) 2008-04-01
JP4826914B2 (ja) 2011-11-30
CN100421226C (zh) 2008-09-24
TW200511572A (en) 2005-03-16
DE602004026737D1 (de) 2010-06-02
US20060019457A1 (en) 2006-01-26
US7012024B2 (en) 2006-03-14
TWI245418B (en) 2005-12-11
US20050037584A1 (en) 2005-02-17
KR100669627B1 (ko) 2007-01-16
EP1656696A4 (de) 2008-07-23
WO2005020282A3 (en) 2006-02-09
EP1656696A2 (de) 2006-05-17
KR20060032662A (ko) 2006-04-17

Similar Documents

Publication Publication Date Title
ATE465511T1 (de) Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode
US7288443B2 (en) Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US8673722B2 (en) Strained channel field effect transistor and the method for fabricating the same
DE602007008611D1 (de) Spannungsverstärkter mos-transistor und verfahren zu seiner herstellung
TW200633125A (en) Semiconductor device and method of semiconductor device
ATE504078T1 (de) Verfahren zur herstellung von cmos-transistoren mit verspanntem halbleiter mit gitterfehlangepassten regionen
ATE535010T1 (de) Verfahren zur herstllung selbstausgerichteten transistortopologien in siliziumkarbid durch verwendung selektiver epitaxie
JP2012504345A5 (de)
WO2006026010A3 (en) Forming abrupt source drain metal gate transistors
WO2006039038A3 (en) Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
TW200633137A (en) Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors
SG137760A1 (en) Method of fabricating a transistor structure
DE602005017490D1 (de) Verfahren zur halbleiterherstellung mit integration einer wegwerf-abstandsschicht in die erhöhte source-/drain-verarbeitung
JP2007536736A5 (de)
ATE475986T1 (de) Verfahren zum herstellen eines halbleiterbauelements
TWI268539B (en) Improved isolation structure for strained channel transistors
GB2456712A (en) Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
WO2007110507A3 (fr) Procede de realisation d'un transistor a effet de champ a grilles auto-alignees
WO2008137478A3 (en) Small geometry mos transistor with thin polycrystalline surface contacts and method for making
WO2008014228A3 (en) Raised sti structure and superdamascene technique for nmosfet performance enhancement with embedded silicon carbon
TW200723410A (en) Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics
TW200618299A (en) Fabrication method of thin film transistor
ATE536634T1 (de) Verfahren zur herstellung eines halbleiterbauelements
TW200513149A (en) Transistor substrate, display device, and method for manufacture
US20130277685A1 (en) Soi transistors with improved source/drain structures with enhanced strain

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties