ATE428143T1 - On-chip system zur verbindung von externen funktionsbausteinen mit einem einzigen parametrierbaren kommunikationsprotokoll - Google Patents

On-chip system zur verbindung von externen funktionsbausteinen mit einem einzigen parametrierbaren kommunikationsprotokoll

Info

Publication number
ATE428143T1
ATE428143T1 AT07300863T AT07300863T ATE428143T1 AT E428143 T1 ATE428143 T1 AT E428143T1 AT 07300863 T AT07300863 T AT 07300863T AT 07300863 T AT07300863 T AT 07300863T AT E428143 T1 ATE428143 T1 AT E428143T1
Authority
AT
Austria
Prior art keywords
messages
parameterizable
communication protocol
functional units
response
Prior art date
Application number
AT07300863T
Other languages
English (en)
Inventor
Cesar Douady
Philippe Boucard
Original Assignee
Arteris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arteris filed Critical Arteris
Application granted granted Critical
Publication of ATE428143T1 publication Critical patent/ATE428143T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Between Computers (AREA)
  • Communication Cables (AREA)
  • Communication Control (AREA)
AT07300863T 2006-04-12 2007-03-14 On-chip system zur verbindung von externen funktionsbausteinen mit einem einzigen parametrierbaren kommunikationsprotokoll ATE428143T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0603248A FR2900017B1 (fr) 2006-04-12 2006-04-12 Systeme d'interconnexions de blocs fonctionnels externes sur puce muni d'un unique protocole parametrable de communication

Publications (1)

Publication Number Publication Date
ATE428143T1 true ATE428143T1 (de) 2009-04-15

Family

ID=37697978

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07300863T ATE428143T1 (de) 2006-04-12 2007-03-14 On-chip system zur verbindung von externen funktionsbausteinen mit einem einzigen parametrierbaren kommunikationsprotokoll

Country Status (5)

Country Link
US (1) US8645557B2 (de)
EP (1) EP1845456B1 (de)
AT (1) ATE428143T1 (de)
DE (1) DE602007000835D1 (de)
FR (1) FR2900017B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2921507B1 (fr) 2007-09-26 2011-04-15 Arteris Dispositif de memoire electronique
US7957400B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Hierarchical network topology
US20100250784A1 (en) * 2009-03-26 2010-09-30 Terascale Supercomputing Inc. Addressing Scheme and Message Routing for a Networked Device
US7957385B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Method and apparatus for packet routing

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2243851A (en) 1940-06-06 1941-06-03 Bell Telephone Labor Inc Wire line transmission
US5764093A (en) 1981-11-28 1998-06-09 Advantest Corporation Variable delay circuit
JPH0388019A (ja) 1989-08-31 1991-04-12 Toshiba Corp データ処理装置
DE69128107T2 (de) * 1990-05-25 1998-02-26 At & T Corp Busanordnung für Speicherzugriff
US5274782A (en) * 1990-08-27 1993-12-28 International Business Machines Corporation Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks
US5313649A (en) 1991-05-28 1994-05-17 International Business Machines Corporation Switch queue structure for one-network parallel processor systems
KR970005124B1 (ko) 1991-08-14 1997-04-12 가부시끼가이샤 아드반테스트 가변지연회로
US5473761A (en) 1991-12-17 1995-12-05 Dell Usa, L.P. Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests
JPH0613857A (ja) 1992-06-25 1994-01-21 Fujitsu Ltd ディレイ調整回路
US5544203A (en) 1993-02-17 1996-08-06 Texas Instruments Incorporated Fine resolution digital delay line with coarse and fine adjustment stages
US5541932A (en) 1994-06-13 1996-07-30 Xerox Corporation Circuit for freezing the data in an interface buffer
US5453982A (en) 1994-08-29 1995-09-26 Hewlett-Packard Company Packet control procedure between a host processor and a peripheral unit
JP2771464B2 (ja) 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5541935A (en) * 1995-05-26 1996-07-30 National Semiconductor Corporation Integrated circuit with test signal buses and test control circuits
EP0752642B1 (de) 1995-07-07 2001-09-26 Sun Microsystems, Inc. Verfahren und Vorrichtung zur dynamischen Berechnung von Füllungsgraden eines synchronen Fifo-Puffer
DE69615471T2 (de) 1995-07-07 2002-05-08 Sun Microsystems Inc Verfahren und Vorrichtung zur dynamischen Berechnung von Füllungsgraden eines synchronen Fifo-Puffer
US5651002A (en) 1995-07-12 1997-07-22 3Com Corporation Internetworking device with enhanced packet header translation and memory
US5784374A (en) 1996-02-06 1998-07-21 Advanced Micro Devices, Inc. Contention resolution system in ATM switch
US6151316A (en) 1997-02-14 2000-11-21 Advanced Micro Devices, Inc. Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller
US6211739B1 (en) 1997-06-03 2001-04-03 Cypress Semiconductor Corp. Microprocessor controlled frequency lock loop for use with an external periodic signal
JP3560780B2 (ja) 1997-07-29 2004-09-02 富士通株式会社 可変遅延回路及び半導体集積回路装置
US6269433B1 (en) 1998-04-29 2001-07-31 Compaq Computer Corporation Memory controller using queue look-ahead to reduce memory latency
US6260152B1 (en) 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6778545B1 (en) 1998-09-24 2004-08-17 Cisco Technology, Inc. DSP voice buffersize negotiation between DSPs for voice packet end devices
EP1549005B1 (de) 1998-12-03 2009-03-11 Secretary of Agency of Industrial Science and Technology Kommunikationsverfahren und -system
US6721309B1 (en) 1999-05-18 2004-04-13 Alcatel Method and apparatus for maintaining packet order integrity in parallel switching engine
US6400720B1 (en) 1999-06-21 2002-06-04 General Instrument Corporation Method for transporting variable length and fixed length packets in a standard digital transmission frame
JP2001084763A (ja) 1999-09-08 2001-03-30 Mitsubishi Electric Corp クロック発生回路およびそれを具備した半導体記憶装置
US6661303B1 (en) 1999-11-30 2003-12-09 International Business Machines Corporation Cross talk suppression in a bidirectional bus
US6651148B2 (en) 2000-05-23 2003-11-18 Canon Kabushiki Kaisha High-speed memory controller for pipelining memory read transactions
AU2001266808A1 (en) 2000-06-09 2001-12-17 The Trustees Of Columbia University In The City Of New York Low latency fifo circuits for mixed asynchronous and synchronous systems
US7266613B1 (en) 2000-08-09 2007-09-04 Microsoft Corporation Fast dynamic measurement of bandwidth in a TCP network environment
DE60031112T8 (de) 2000-08-23 2007-09-06 Sony Deutschland Gmbh Fernbedienung eines Hausnetzwerks mittels elektronischer Post
FR2814007B1 (fr) 2000-09-08 2003-01-31 France Telecom Oscillateur commande en tension
US6850542B2 (en) 2000-11-14 2005-02-01 Broadcom Corporation Linked network switch configuration
KR100467643B1 (ko) 2000-12-28 2005-01-24 엘지전자 주식회사 무선 랜에서의 멀티미디어 데이터 전송 방법
US6615319B2 (en) * 2000-12-29 2003-09-02 Intel Corporation Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture
SE0101015D0 (sv) * 2001-03-21 2001-03-21 Ericsson Telefon Ab L M Interconection of signalling nodes
US20040128413A1 (en) 2001-06-08 2004-07-01 Tiberiu Chelcea Low latency fifo circuits for mixed asynchronous and synchronous systems
US7164678B2 (en) 2001-06-25 2007-01-16 Intel Corporation Control of processing order for received network packets
EP1282265A3 (de) * 2001-07-26 2003-06-18 Allied Telesis Kabushiki Kaisha Medienumsetzer mit Test Manager
KR100454922B1 (ko) * 2001-10-31 2004-11-15 삼성전자주식회사 실시간 교통정보를 제공하는 네비게이션 시스템 및 그에의한 교통정보 처리 방법
US6886048B2 (en) 2001-11-15 2005-04-26 Hewlett-Packard Development Company, L.P. Techniques for processing out-of-order requests in a processor-based system
US6759911B2 (en) 2001-11-19 2004-07-06 Mcron Technology, Inc. Delay-locked loop circuit and method using a ring oscillator and counter-based delay
US7292594B2 (en) 2002-06-10 2007-11-06 Lsi Corporation Weighted fair share scheduler for large input-buffered high-speed cross-point packet/cell switches
US6970979B2 (en) * 2002-06-28 2005-11-29 Sun Microsystems, Inc. System with virtual address networks and split ownership and access right coherence mechanism
US7277449B2 (en) 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US6915361B2 (en) 2002-10-03 2005-07-05 International Business Machines Corporation Optimal buffered routing path constructions for single and multiple clock domains systems
WO2004032535A2 (en) * 2002-10-04 2004-04-15 M-Stack Limited Access stratum manager
JP4560409B2 (ja) * 2002-10-08 2010-10-13 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ データを交換する集積回路および方法
US20040088472A1 (en) 2002-10-31 2004-05-06 Nystuen John M. Multi-mode memory controller
US6812760B1 (en) 2003-07-02 2004-11-02 Micron Technology, Inc. System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits
FR2857114B1 (fr) 2003-07-04 2005-09-30 Arteris Systeme et procede de communication entre des modules
FR2858148B1 (fr) 2003-07-22 2005-09-30 Arteris Dispositif et procede de transmission d'un message
FR2858895B1 (fr) 2003-08-13 2006-05-05 Arteris Procede et dispositif de gestion de priorite lors de la transmission d'un message
FR2860663B1 (fr) 2003-10-01 2006-09-01 Arteris Dispositif de retard numerique, oscillateur numerique generateur de signal d'horloge, et interface memoire
FR2862457B1 (fr) 2003-11-13 2006-02-24 Arteris Systeme et procede de transmission d'une sequence de messages dans un reseau d'interconnexions.
FR2863377B1 (fr) 2003-12-09 2006-02-17 Arteris Procede de gestion d'un dispositif de memorisation de donnees organisees en file d'attente, et dispositif associe
FR2865334B1 (fr) 2004-01-21 2006-03-03 Arteris Procede et systeme de transmission de messages dans un reseau d'interconnexions.
FR2867338B1 (fr) 2004-03-02 2007-08-10 Arteris Procede et dispositif de commutation entre des agents
US7747017B2 (en) * 2004-12-01 2010-06-29 Motorola, Inc. Method and apparatus for end-to-end clear transport protocol
FR2887093B1 (fr) 2005-06-10 2007-08-31 Arteris Sa Systeme et procede de transmission de donnees dans un circuit electronique
FR2890766B1 (fr) 2005-09-12 2007-11-30 Arteris Sa Systeme et procede de communication asynchrone sur circuit, entre des sous-circuits synchrones
FR2893471B1 (fr) 2005-11-16 2008-01-25 Arteris Sa Systeme et procede de routage statique de flux de paquets de donnees dans un reseau d'interconnexion

Also Published As

Publication number Publication date
DE602007000835D1 (de) 2009-05-20
US8645557B2 (en) 2014-02-04
FR2900017B1 (fr) 2008-10-31
US20070245044A1 (en) 2007-10-18
EP1845456B1 (de) 2009-04-08
FR2900017A1 (fr) 2007-10-19
EP1845456A1 (de) 2007-10-17

Similar Documents

Publication Publication Date Title
WO2009018418A3 (en) Systems, methods, and computer program products for distributing application or higher layer communications network signaling entity operational status information among session initiation protocol (sip) entities
PL1813088T3 (pl) Sposób oraz system trasowania w sieciach komunikacyjnych między pierwszym węzłem a drugim węzłem
CN110417783B (zh) 一种基于物联网的数据传输方法、装置、储存介质及终端
WO2008045656A3 (en) Upgrading mesh access points in a wireless mesh network
WO2011056714A3 (en) Employing overlays for securing connections across networks
CN104737519A (zh) 用于软件定义网络(sdn)的通用网络控制器的系统和设备
CN104468368B (zh) 配置bgp邻居的方法及装置
RU2011119536A (ru) Способ применения экземпляра службы к сети mpls (варианты) и сеть mpls
WO2008067446A3 (en) Ip based notification of device management operations in a network
GB0906411D0 (en) Method and system for data transmission
FI20085193A0 (fi) Toistinsolmun yhteydenhallinta
CN104243281A (zh) 基于移动互联网的语音通信方法
WO2007133854A3 (en) System and method for distributing proxying error information in wireless networks
CN109586958A (zh) 双系统装置的配置管理方法及双系统装置
ATE428143T1 (de) On-chip system zur verbindung von externen funktionsbausteinen mit einem einzigen parametrierbaren kommunikationsprotokoll
CN102647432A (zh) 一种认证信息传输方法、装置及认证中间件
CN104506405B (zh) 跨域访问的方法及装置
FI20045234A0 (fi) Datan lähetys viestintäjärjestelmässä
WO2009007956A3 (en) A method for initiating a connection between communication devices of at least two parties
CN104320286A (zh) 无线路由器简便配置装置及采用该装置实现的路由器配置方法
MX2007005008A (es) Un procedimiento para registrar una terminal de comunicacion movil en una red de area local.
NO20064249L (no) Overforing av kommunikasjon mellom dataoverforingsnett
ATE375052T1 (de) Vorreservierung von ressourcen für verbindungswege in einem kommunikationsnetz an kommunikation von anschriften von päckchen oder von etiketten
CN101510901B (zh) 一种分布式设备间的通信方法、通信设备和通信系统
CN105991421A (zh) 一种集团通信圈内的消息推送方法、设备和系统

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties