DE602007000835D1 - On-Chip System zur Verbindung von externen Funktionsbausteinen mit einem einzigen parametrierbaren Kommunikationsprotokoll - Google Patents

On-Chip System zur Verbindung von externen Funktionsbausteinen mit einem einzigen parametrierbaren Kommunikationsprotokoll

Info

Publication number
DE602007000835D1
DE602007000835D1 DE602007000835T DE602007000835T DE602007000835D1 DE 602007000835 D1 DE602007000835 D1 DE 602007000835D1 DE 602007000835 T DE602007000835 T DE 602007000835T DE 602007000835 T DE602007000835 T DE 602007000835T DE 602007000835 D1 DE602007000835 D1 DE 602007000835D1
Authority
DE
Germany
Prior art keywords
messages
parameterizable
communication protocol
response
function blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602007000835T
Other languages
English (en)
Inventor
Cesar Douady
Philippe Boucard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arteris SAS
Original Assignee
Arteris SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arteris SAS filed Critical Arteris SAS
Publication of DE602007000835D1 publication Critical patent/DE602007000835D1/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Communication Cables (AREA)
  • Information Transfer Between Computers (AREA)
DE602007000835T 2006-04-12 2007-03-14 On-Chip System zur Verbindung von externen Funktionsbausteinen mit einem einzigen parametrierbaren Kommunikationsprotokoll Expired - Fee Related DE602007000835D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0603248A FR2900017B1 (fr) 2006-04-12 2006-04-12 Systeme d'interconnexions de blocs fonctionnels externes sur puce muni d'un unique protocole parametrable de communication

Publications (1)

Publication Number Publication Date
DE602007000835D1 true DE602007000835D1 (de) 2009-05-20

Family

ID=37697978

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007000835T Expired - Fee Related DE602007000835D1 (de) 2006-04-12 2007-03-14 On-Chip System zur Verbindung von externen Funktionsbausteinen mit einem einzigen parametrierbaren Kommunikationsprotokoll

Country Status (5)

Country Link
US (1) US8645557B2 (de)
EP (1) EP1845456B1 (de)
AT (1) ATE428143T1 (de)
DE (1) DE602007000835D1 (de)
FR (1) FR2900017B1 (de)

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* Cited by examiner, † Cited by third party
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FR2921507B1 (fr) 2007-09-26 2011-04-15 Arteris Dispositif de memoire electronique
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US7957385B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Method and apparatus for packet routing
US7957400B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Hierarchical network topology

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Also Published As

Publication number Publication date
US20070245044A1 (en) 2007-10-18
FR2900017B1 (fr) 2008-10-31
US8645557B2 (en) 2014-02-04
EP1845456B1 (de) 2009-04-08
FR2900017A1 (fr) 2007-10-19
EP1845456A1 (de) 2007-10-17
ATE428143T1 (de) 2009-04-15

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