ATE401667T1 - Verfahren zum herstellen eines transistors mit selbst justierten doppel-gates durch schrumpfung der gatestruktur - Google Patents
Verfahren zum herstellen eines transistors mit selbst justierten doppel-gates durch schrumpfung der gatestrukturInfo
- Publication number
- ATE401667T1 ATE401667T1 AT06124271T AT06124271T ATE401667T1 AT E401667 T1 ATE401667 T1 AT E401667T1 AT 06124271 T AT06124271 T AT 06124271T AT 06124271 T AT06124271 T AT 06124271T AT E401667 T1 ATE401667 T1 AT E401667T1
- Authority
- AT
- Austria
- Prior art keywords
- layer
- grid
- stack
- zone
- motif
- Prior art date
Links
- 239000000463 material Substances 0.000 abstract 15
- 239000004065 semiconductor Substances 0.000 abstract 13
- 238000005530 etching Methods 0.000 abstract 9
- 238000000151 deposition Methods 0.000 abstract 6
- 239000007769 metal material Substances 0.000 abstract 3
- 238000004377 microelectronic Methods 0.000 abstract 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000001312 dry etching Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000000873 masking effect Effects 0.000 abstract 2
- 238000001020 plasma etching Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0553510A FR2893762B1 (fr) | 2005-11-18 | 2005-11-18 | Procede de realisation de transistor a double grilles auto-alignees par reduction de motifs de grille |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE401667T1 true ATE401667T1 (de) | 2008-08-15 |
Family
ID=36608627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06124271T ATE401667T1 (de) | 2005-11-18 | 2006-11-17 | Verfahren zum herstellen eines transistors mit selbst justierten doppel-gates durch schrumpfung der gatestruktur |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20090079004A1 (de) |
| EP (2) | EP1788635B1 (de) |
| AT (1) | ATE401667T1 (de) |
| DE (1) | DE602006001828D1 (de) |
| FR (1) | FR2893762B1 (de) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2911004B1 (fr) * | 2006-12-28 | 2009-05-15 | Commissariat Energie Atomique | Procede de realisation de transistors a double-grille asymetriques permettant la realisation de transistors a double-grille asymetriques et symetriques sur un meme substrat |
| US7671418B2 (en) * | 2007-09-14 | 2010-03-02 | Advanced Micro Devices, Inc. | Double layer stress for multiple gate transistors |
| FR2937463B1 (fr) * | 2008-10-17 | 2010-12-24 | Commissariat Energie Atomique | Procede de fabrication de composants empiles et auto-alignes sur un substrat |
| FR2947384B1 (fr) * | 2009-06-25 | 2012-03-30 | Commissariat Energie Atomique | Procede de realisation d'un transistor a source et drain metalliques |
| FR2970813B1 (fr) * | 2011-01-24 | 2013-09-27 | Commissariat Energie Atomique | Dispositif a effet de champ muni d'une zone barrière de diffusion de dopants localisée et procédé de réalisation |
| US9343589B2 (en) * | 2014-01-22 | 2016-05-17 | Globalfoundries Inc. | Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures |
| FR3064398B1 (fr) * | 2017-03-21 | 2019-06-07 | Soitec | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure |
| CN112490289B (zh) * | 2020-11-22 | 2022-08-19 | 复旦大学 | 基于自对准结构的叠层沟道纳米片晶体管及其制备方法 |
| CN113394127B (zh) * | 2021-06-16 | 2022-04-19 | 长江存储科技有限责任公司 | 3d存储器桥接结构的关键尺寸的监测方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814537A (en) * | 1996-12-18 | 1998-09-29 | Sharp Microelectronics Technology,Inc. | Method of forming transistor electrodes from directionally deposited silicide |
| US6277679B1 (en) * | 1998-11-25 | 2001-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing thin film transistor |
| US6531713B1 (en) * | 1999-03-19 | 2003-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and manufacturing method thereof |
| US6365465B1 (en) * | 1999-03-19 | 2002-04-02 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques |
| DE19924571C2 (de) * | 1999-05-28 | 2001-03-15 | Siemens Ag | Verfahren zur Herstellung eines Doppel-Gate-MOSFET-Transistors |
| US6320236B1 (en) * | 1999-10-06 | 2001-11-20 | Advanced Micro Devices, Inc. | Optimization of logic gates with criss-cross implants to form asymmetric channel regions |
| US20020090758A1 (en) * | 2000-09-19 | 2002-07-11 | Silicon Genesis Corporation | Method and resulting device for manufacturing for double gated transistors |
| US6596597B2 (en) * | 2001-06-12 | 2003-07-22 | International Business Machines Corporation | Method of manufacturing dual gate logic devices |
| DE10208881B4 (de) * | 2002-03-01 | 2007-06-28 | Forschungszentrum Jülich GmbH | Selbstjustierendes Verfahren zur Herstellung eines Doppel-Gate MOSFET sowie durch dieses Verfahren hergestellter Doppel-Gate MOSFET |
| FR2838238B1 (fr) * | 2002-04-08 | 2005-04-15 | St Microelectronics Sa | Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant |
| US6905976B2 (en) * | 2003-05-06 | 2005-06-14 | International Business Machines Corporation | Structure and method of forming a notched gate field effect transistor |
| US20050006640A1 (en) * | 2003-06-26 | 2005-01-13 | Jackson Warren B. | Polymer-based memory element |
| US7518195B2 (en) * | 2004-10-21 | 2009-04-14 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
| US20070228480A1 (en) * | 2006-04-03 | 2007-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS device having PMOS and NMOS transistors with different gate structures |
-
2005
- 2005-11-18 FR FR0553510A patent/FR2893762B1/fr not_active Expired - Fee Related
-
2006
- 2006-11-17 EP EP06124271A patent/EP1788635B1/de active Active
- 2006-11-17 EP EP07118245A patent/EP1881533A3/de not_active Withdrawn
- 2006-11-17 AT AT06124271T patent/ATE401667T1/de not_active IP Right Cessation
- 2006-11-17 DE DE602006001828T patent/DE602006001828D1/de active Active
- 2006-11-17 US US11/561,174 patent/US20090079004A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1788635A1 (de) | 2007-05-23 |
| FR2893762B1 (fr) | 2007-12-21 |
| EP1788635B1 (de) | 2008-07-16 |
| DE602006001828D1 (de) | 2008-08-28 |
| EP1881533A2 (de) | 2008-01-23 |
| FR2893762A1 (fr) | 2007-05-25 |
| US20090079004A1 (en) | 2009-03-26 |
| EP1881533A3 (de) | 2008-02-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE401667T1 (de) | Verfahren zum herstellen eines transistors mit selbst justierten doppel-gates durch schrumpfung der gatestruktur | |
| JP2006270107A5 (de) | ||
| US9331200B1 (en) | Semiconductor device and method for fabricating the same | |
| US20180047848A1 (en) | Method of fabricating semiconductor device | |
| JP2011044517A5 (de) | ||
| CN106340455A (zh) | 半导体元件及其制作方法 | |
| GB2579463A (en) | Utilizing multiplayer gate spacer to reduce erosion of semiconductor fin during spacer patterning | |
| JP2009528701A5 (de) | ||
| JP2009514247A5 (de) | ||
| ATE544178T1 (de) | Halbleiterbauelemente und verfahren zur herstellung | |
| CN103515321B (zh) | 半导体器件的侧墙形成方法 | |
| JP2012516036A5 (de) | ||
| JP2009506549A5 (de) | ||
| US7436005B2 (en) | Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor | |
| JP2008520097A5 (de) | ||
| JP2006210927A5 (de) | ||
| JP2009027002A5 (de) | ||
| JP2009527928A (ja) | ソース／ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 | |
| JP2006147789A5 (de) | ||
| JP2009527928A5 (de) | ||
| ATE515791T1 (de) | Herstellungsverfahren für eine halbleitervorrichtung | |
| TW200535975A (en) | Enhancing strained device performance by use of multi-narrow section layout | |
| TW200710946A (en) | Method for manufacturing semiconductor apparatus and the semiconductor apparatus | |
| JP2021507507A5 (de) | ||
| JP2009054999A5 (de) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |