ATE315237T1 - Eingebaute testschaltung zur prüfung von phasenregelkreisschaltung - Google Patents

Eingebaute testschaltung zur prüfung von phasenregelkreisschaltung

Info

Publication number
ATE315237T1
ATE315237T1 AT01976284T AT01976284T ATE315237T1 AT E315237 T1 ATE315237 T1 AT E315237T1 AT 01976284 T AT01976284 T AT 01976284T AT 01976284 T AT01976284 T AT 01976284T AT E315237 T1 ATE315237 T1 AT E315237T1
Authority
AT
Austria
Prior art keywords
frequency
built
phase control
circuit
test circuit
Prior art date
Application number
AT01976284T
Other languages
English (en)
Inventor
Russell Ott
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE315237T1 publication Critical patent/ATE315237T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318328—Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
AT01976284T 2000-10-17 2001-10-09 Eingebaute testschaltung zur prüfung von phasenregelkreisschaltung ATE315237T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/690,267 US6294935B1 (en) 2000-10-17 2000-10-17 Built-in-self-test circuitry for testing a phase locked loop circuit

Publications (1)

Publication Number Publication Date
ATE315237T1 true ATE315237T1 (de) 2006-02-15

Family

ID=24771787

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01976284T ATE315237T1 (de) 2000-10-17 2001-10-09 Eingebaute testschaltung zur prüfung von phasenregelkreisschaltung

Country Status (6)

Country Link
US (1) US6294935B1 (de)
EP (1) EP1368671B1 (de)
JP (1) JP3923896B2 (de)
AT (1) ATE315237T1 (de)
DE (1) DE60116516T2 (de)
WO (1) WO2002033433A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3916512B2 (ja) * 2002-06-04 2007-05-16 沖電気工業株式会社 Ｐｌｌ内蔵回路の評価方法及びｐｌｌ内蔵回路の評価システム
DE60303976D1 (de) * 2003-05-07 2006-05-11 St Microelectronics Srl Eingebettete Testschaltung für Phasenregelschleife sowie dazugehörige Verfahren und Rechnerprogramm
US7061223B2 (en) * 2003-06-26 2006-06-13 International Business Machines Corporation PLL manufacturing test apparatus
US7151399B2 (en) * 2004-02-02 2006-12-19 Toshiba America Electronic Components, Inc. System and method for generating multiple clock signals
US7194670B2 (en) * 2004-02-13 2007-03-20 International Business Machines Corp. Command multiplier for built-in-self-test
JP4668591B2 (ja) * 2004-11-25 2011-04-13 富士通株式会社 高周波数カウンタ回路
US20060187899A1 (en) * 2005-02-02 2006-08-24 Gemtek Systems, Inc. System of providing communication service via client representatives and the method of the same
US7692419B1 (en) * 2005-09-26 2010-04-06 Cypress Semiconductor Corporation Method and apparatus for enhanced frequency measurement
US20070226567A1 (en) * 2006-03-23 2007-09-27 Gorman Kevin W High speed bist utilizing clock multiplication
JP5006417B2 (ja) 2010-01-28 2012-08-22 日本電波工業株式会社 Ｐｌｌ発振回路
JP6204218B2 (ja) * 2014-02-17 2017-09-27 パナソニック株式会社 信号生成回路
TWI625534B (zh) * 2015-12-21 2018-06-01 瑞昱半導體股份有限公司 透過掃描測試的掃描鏈所執行的除錯方法及相關電路系統
US11218153B1 (en) 2020-10-29 2022-01-04 Nxp B.V. Configurable built-in self-test for an all digital phase locked loop

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381085A (en) * 1993-07-06 1995-01-10 Motorola, Inc. Phase lock loop with self test circuitry and method for using the same
US5729151A (en) * 1996-03-11 1998-03-17 Motorola Inc. System and method for testing a phase locked loop in an integrated circuit
US6005904A (en) * 1997-10-16 1999-12-21 Oasis Design, Inc. Phase-locked loop with protected output during instances when the phase-locked loop is unlocked
CA2220622C (en) * 1997-11-03 2004-03-30 Aubin P. J. Roy Method and circuit for built in self test of phase locked loops
US6121816A (en) * 1999-04-23 2000-09-19 Semtech Corporation Slave clock generation system and method for synchronous telecommunications networks
US6201448B1 (en) * 1999-12-28 2001-03-13 Intel Corporation Method and apparatus to reduce clock jitter of an on-chip clock signal

Also Published As

Publication number Publication date
DE60116516T2 (de) 2006-08-24
WO2002033433A2 (en) 2002-04-25
US6294935B1 (en) 2001-09-25
WO2002033433A3 (en) 2003-10-09
EP1368671A2 (de) 2003-12-10
JP3923896B2 (ja) 2007-06-06
JP2004511993A (ja) 2004-04-15
EP1368671B1 (de) 2006-01-04
DE60116516D1 (de) 2006-03-30

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Legal Events

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