ATE314729T1 - Herstellungsprozess für verarmungs-mosfet- bauelemente, silizidierte source-und drainkontakte - Google Patents
Herstellungsprozess für verarmungs-mosfet- bauelemente, silizidierte source-und drainkontakteInfo
- Publication number
- ATE314729T1 ATE314729T1 AT01967502T AT01967502T ATE314729T1 AT E314729 T1 ATE314729 T1 AT E314729T1 AT 01967502 T AT01967502 T AT 01967502T AT 01967502 T AT01967502 T AT 01967502T AT E314729 T1 ATE314729 T1 AT E314729T1
- Authority
- AT
- Austria
- Prior art keywords
- source
- depupperation
- silicidated
- manufacturing process
- drain contacts
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000004913 activation Effects 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/926—Dummy metallization
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Silicates, Zeolites, And Molecular Sieves (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/672,185 US6440808B1 (en) | 2000-09-28 | 2000-09-28 | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly |
PCT/GB2001/004154 WO2002027799A2 (en) | 2000-09-28 | 2001-09-17 | Process for the fabrication of mosfet devices depletion, silicided source and drain junctions |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE314729T1 true ATE314729T1 (de) | 2006-01-15 |
Family
ID=24697488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT01967502T ATE314729T1 (de) | 2000-09-28 | 2001-09-17 | Herstellungsprozess für verarmungs-mosfet- bauelemente, silizidierte source-und drainkontakte |
Country Status (9)
Country | Link |
---|---|
US (1) | US6440808B1 (de) |
EP (1) | EP1320878B1 (de) |
JP (1) | JP4027064B2 (de) |
KR (1) | KR100537580B1 (de) |
AT (1) | ATE314729T1 (de) |
AU (1) | AU2001287877A1 (de) |
DE (1) | DE60116342T2 (de) |
TW (1) | TW517288B (de) |
WO (1) | WO2002027799A2 (de) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6656764B1 (en) * | 2002-05-15 | 2003-12-02 | Taiwan Semiconductor Manufacturing Company | Process for integration of a high dielectric constant gate insulator layer in a CMOS device |
US6790733B1 (en) * | 2003-03-28 | 2004-09-14 | International Business Machines Corporation | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer |
JP5001388B2 (ja) * | 2003-06-24 | 2012-08-15 | 東京エレクトロン株式会社 | 被処理体処理装置の圧力制御方法 |
JP4833512B2 (ja) * | 2003-06-24 | 2011-12-07 | 東京エレクトロン株式会社 | 被処理体処理装置、被処理体処理方法及び被処理体搬送方法 |
CN1309023C (zh) * | 2003-08-22 | 2007-04-04 | 南亚科技股份有限公司 | 镶嵌式闸极制程 |
US7332421B2 (en) * | 2003-12-31 | 2008-02-19 | Dongbu Electronics Co., Ltd. | Method of fabricating gate electrode of semiconductor device |
US7479684B2 (en) | 2004-11-02 | 2009-01-20 | International Business Machines Corporation | Field effect transistor including damascene gate with an internal spacer structure |
KR100680505B1 (ko) * | 2005-12-14 | 2007-02-08 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
KR100715272B1 (ko) | 2006-04-21 | 2007-05-08 | 삼성전자주식회사 | 게이트 구조물의 형성 방법 및 이를 이용한 반도체 장치의제조 방법 |
US20080079084A1 (en) * | 2006-09-28 | 2008-04-03 | Micron Technology, Inc. | Enhanced mobility MOSFET devices |
US7435636B1 (en) | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
US7585716B2 (en) * | 2007-06-27 | 2009-09-08 | International Business Machines Corporation | High-k/metal gate MOSFET with reduced parasitic capacitance |
JP5462161B2 (ja) * | 2007-07-20 | 2014-04-02 | アイメック | Iii−v族mesfetでのダマシンコンタクト製造方法 |
US7745295B2 (en) * | 2007-11-26 | 2010-06-29 | Micron Technology, Inc. | Methods of forming memory cells |
US20100038705A1 (en) * | 2008-08-12 | 2010-02-18 | International Business Machines Corporation | Field effect device with gate electrode edge enhanced gate dielectric and method for fabrication |
US8048733B2 (en) * | 2009-10-09 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a gate structure |
DE102010003451B4 (de) | 2010-03-30 | 2013-12-24 | Globalfoundries Dresden Module One Llc & Co. Kg | Austauschgateverfahren für Metallgatestapel mit großem ε durch Vermeiden eines Polierprozesses zum Freilegen des Platzhaltermaterials |
CN102569076B (zh) * | 2010-12-08 | 2015-06-10 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US8759219B2 (en) * | 2011-01-24 | 2014-06-24 | United Microelectronics Corp. | Planarization method applied in process of manufacturing semiconductor component |
US9385044B2 (en) * | 2012-12-31 | 2016-07-05 | Texas Instruments Incorporated | Replacement gate process |
US9184089B2 (en) | 2013-10-04 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism of forming a trench structure |
US9396986B2 (en) * | 2013-10-04 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism of forming a trench structure |
TWI689040B (zh) | 2017-02-02 | 2020-03-21 | 聯華電子股份有限公司 | 半導體元件及其製造方法 |
CN109585546A (zh) * | 2017-09-29 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US11329164B2 (en) | 2018-06-06 | 2022-05-10 | The University Of Hong Kong | Metal-oxide-semiconductor field-effect transistor with a cold source |
CN113745314B (zh) * | 2021-07-16 | 2024-04-02 | 中国科学院微电子研究所 | 冷源mos晶体管及制作方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168072A (en) * | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
US6063677A (en) * | 1996-10-28 | 2000-05-16 | Texas Instruments Incorporated | Method of forming a MOSFET using a disposable gate and raised source and drain |
US6133106A (en) * | 1998-02-23 | 2000-10-17 | Sharp Laboratories Of America, Inc. | Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement |
US6399432B1 (en) * | 1998-11-24 | 2002-06-04 | Philips Semiconductors Inc. | Process to control poly silicon profiles in a dual doped poly silicon process |
US6277707B1 (en) * | 1998-12-16 | 2001-08-21 | Lsi Logic Corporation | Method of manufacturing semiconductor device having a recessed gate structure |
US6284613B1 (en) * | 1999-11-05 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a T-gate for better salicidation |
TW543102B (en) * | 2000-01-04 | 2003-07-21 | Taiwan Semiconductor Mfg | Manufacturing method of metal-oxide-semiconductor device |
US6319807B1 (en) * | 2000-02-07 | 2001-11-20 | United Microelectronics Corp. | Method for forming a semiconductor device by using reverse-offset spacer process |
US6303447B1 (en) * | 2000-02-11 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an extended metal gate using a damascene process |
US6271094B1 (en) * | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
US6303418B1 (en) * | 2000-06-30 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer |
-
2000
- 2000-09-28 US US09/672,185 patent/US6440808B1/en not_active Expired - Fee Related
-
2001
- 2001-09-17 KR KR10-2003-7004228A patent/KR100537580B1/ko not_active IP Right Cessation
- 2001-09-17 AU AU2001287877A patent/AU2001287877A1/en not_active Abandoned
- 2001-09-17 WO PCT/GB2001/004154 patent/WO2002027799A2/en active IP Right Grant
- 2001-09-17 AT AT01967502T patent/ATE314729T1/de not_active IP Right Cessation
- 2001-09-17 DE DE60116342T patent/DE60116342T2/de not_active Expired - Lifetime
- 2001-09-17 EP EP01967502A patent/EP1320878B1/de not_active Expired - Lifetime
- 2001-09-20 JP JP2001286248A patent/JP4027064B2/ja not_active Expired - Fee Related
- 2001-09-25 TW TW090123593A patent/TW517288B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1320878B1 (de) | 2005-12-28 |
TW517288B (en) | 2003-01-11 |
DE60116342D1 (de) | 2006-02-02 |
AU2001287877A1 (en) | 2002-04-08 |
WO2002027799A2 (en) | 2002-04-04 |
KR100537580B1 (ko) | 2005-12-20 |
JP2002151690A (ja) | 2002-05-24 |
JP4027064B2 (ja) | 2007-12-26 |
KR20030033081A (ko) | 2003-04-26 |
EP1320878A2 (de) | 2003-06-25 |
DE60116342T2 (de) | 2006-08-03 |
WO2002027799A3 (en) | 2002-11-21 |
US6440808B1 (en) | 2002-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |