ATE307377T1 - Ram speicher - Google Patents
Ram speicherInfo
- Publication number
- ATE307377T1 ATE307377T1 AT00401972T AT00401972T ATE307377T1 AT E307377 T1 ATE307377 T1 AT E307377T1 AT 00401972 T AT00401972 T AT 00401972T AT 00401972 T AT00401972 T AT 00401972T AT E307377 T1 ATE307377 T1 AT E307377T1
- Authority
- AT
- Austria
- Prior art keywords
- sel
- row
- cell
- read
- write
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Electrophonic Musical Instruments (AREA)
- Valve Device For Special Equipments (AREA)
- Surgical Instruments (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9908947A FR2808114B1 (fr) | 1999-07-09 | 1999-07-09 | Memoire ram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE307377T1 true ATE307377T1 (de) | 2005-11-15 |
Family
ID=9547944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT00401972T ATE307377T1 (de) | 1999-07-09 | 2000-07-07 | Ram speicher |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6366504B1 (de) |
| EP (1) | EP1067556B1 (de) |
| AT (1) | ATE307377T1 (de) |
| DE (1) | DE60023213T2 (de) |
| FR (1) | FR2808114B1 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6580635B1 (en) * | 2002-04-25 | 2003-06-17 | Hewlett-Packard Development Company, L.P. | Bitline splitter |
| US6657886B1 (en) * | 2002-05-07 | 2003-12-02 | International Business Machines Corporation | Split local and continuous bitline for fast domino read SRAM |
| US6741493B1 (en) * | 2002-11-07 | 2004-05-25 | International Business Machines Corporation | Split local and continuous bitline requiring fewer wires |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729501A (en) * | 1995-09-08 | 1998-03-17 | International Business Machines Corporation | High Speed SRAM with or-gate sense |
| JPH10162580A (ja) * | 1996-11-29 | 1998-06-19 | Mitsubishi Electric Corp | スタティック型半導体記憶装置とその動作方法 |
| US5901079A (en) * | 1997-01-13 | 1999-05-04 | International Business Machines Corporation | Skewed memory cell apparatus and method |
| DE69727939D1 (de) * | 1997-11-28 | 2004-04-08 | St Microelectronics Srl | RAM-Speicherzelle mit niedriger Leistungsaufnahme und einer einzigen Bitleitung |
| TW371761B (en) * | 1998-03-13 | 1999-10-11 | Winbond Electronics Corp | SRAM structure using common bit-line |
| US6240009B1 (en) * | 2000-02-02 | 2001-05-29 | Hewlett-Packard Company | Asymmetric ram cell |
-
1999
- 1999-07-09 FR FR9908947A patent/FR2808114B1/fr not_active Expired - Fee Related
-
2000
- 2000-07-07 AT AT00401972T patent/ATE307377T1/de not_active IP Right Cessation
- 2000-07-07 EP EP00401972A patent/EP1067556B1/de not_active Expired - Lifetime
- 2000-07-07 DE DE60023213T patent/DE60023213T2/de not_active Expired - Lifetime
- 2000-07-07 US US09/612,061 patent/US6366504B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1067556A1 (de) | 2001-01-10 |
| FR2808114A1 (fr) | 2001-10-26 |
| EP1067556B1 (de) | 2005-10-19 |
| DE60023213T2 (de) | 2006-07-06 |
| FR2808114B1 (fr) | 2002-07-12 |
| US6366504B1 (en) | 2002-04-02 |
| DE60023213D1 (de) | 2006-03-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |