ATE239936T1 - Verfahren und vorrichtung zum schreiben und lesen eines pufferspeichers - Google Patents

Verfahren und vorrichtung zum schreiben und lesen eines pufferspeichers

Info

Publication number
ATE239936T1
ATE239936T1 AT00962165T AT00962165T ATE239936T1 AT E239936 T1 ATE239936 T1 AT E239936T1 AT 00962165 T AT00962165 T AT 00962165T AT 00962165 T AT00962165 T AT 00962165T AT E239936 T1 ATE239936 T1 AT E239936T1
Authority
AT
Austria
Prior art keywords
buffer memory
writing
reading
addressing device
read
Prior art date
Application number
AT00962165T
Other languages
English (en)
Inventor
Peter Hober
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE239936T1 publication Critical patent/ATE239936T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Static Random-Access Memory (AREA)
AT00962165T 1999-07-28 2000-07-28 Verfahren und vorrichtung zum schreiben und lesen eines pufferspeichers ATE239936T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19935499 1999-07-28
PCT/DE2000/002501 WO2001009710A1 (de) 1999-07-28 2000-07-28 Verfahren und vorrichtung zum schreiben und lesen eines pufferspeichers

Publications (1)

Publication Number Publication Date
ATE239936T1 true ATE239936T1 (de) 2003-05-15

Family

ID=7916389

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00962165T ATE239936T1 (de) 1999-07-28 2000-07-28 Verfahren und vorrichtung zum schreiben und lesen eines pufferspeichers

Country Status (7)

Country Link
EP (1) EP1116098B1 (de)
JP (1) JP2003506813A (de)
KR (1) KR20010075263A (de)
CN (1) CN1159646C (de)
AT (1) ATE239936T1 (de)
DE (1) DE50002059D1 (de)
WO (1) WO2001009710A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1294482C (zh) * 2004-06-08 2007-01-10 大唐微电子技术有限公司 支持16位和32位字宽存储器的启动方法及装置
US9189199B2 (en) 2012-12-06 2015-11-17 Nvidia Corporation Folded FIFO memory generator
KR102521298B1 (ko) * 2018-02-14 2023-04-14 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0299264A3 (de) * 1987-07-15 1991-03-20 Advanced Micro Devices, Inc. Warteschlangengerät für die Verarbeitung von Datenwörtern/Instruktionen variabler Länge in einem einzigen Taktzyklus
GB2291230B (en) * 1992-10-15 1996-10-16 Fujitsu Ltd Fifo memory devices

Also Published As

Publication number Publication date
CN1319202A (zh) 2001-10-24
JP2003506813A (ja) 2003-02-18
EP1116098A1 (de) 2001-07-18
EP1116098B1 (de) 2003-05-07
CN1159646C (zh) 2004-07-28
WO2001009710A1 (de) 2001-02-08
KR20010075263A (ko) 2001-08-09
DE50002059D1 (de) 2003-06-12

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