ATE174139T1 - Buszuweisungssystem für digitalsignalprozessoren - Google Patents

Buszuweisungssystem für digitalsignalprozessoren

Info

Publication number
ATE174139T1
ATE174139T1 AT95931282T AT95931282T ATE174139T1 AT E174139 T1 ATE174139 T1 AT E174139T1 AT 95931282 T AT95931282 T AT 95931282T AT 95931282 T AT95931282 T AT 95931282T AT E174139 T1 ATE174139 T1 AT E174139T1
Authority
AT
Austria
Prior art keywords
digital signal
signal processors
allocation system
bus
bus allocation
Prior art date
Application number
AT95931282T
Other languages
German (de)
English (en)
Inventor
David John Spreadbury
Clive Russell Irving
Original Assignee
Ionica Int Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ionica Int Ltd filed Critical Ionica Int Ltd
Application granted granted Critical
Publication of ATE174139T1 publication Critical patent/ATE174139T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
  • Surgical Instruments (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Orthopedics, Nursing, And Contraception (AREA)
  • Information Transfer Systems (AREA)
  • Chemical Or Physical Treatment Of Fibers (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
AT95931282T 1994-09-16 1995-09-08 Buszuweisungssystem für digitalsignalprozessoren ATE174139T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9418753A GB9418753D0 (en) 1994-09-16 1994-09-16 Process circuitry

Publications (1)

Publication Number Publication Date
ATE174139T1 true ATE174139T1 (de) 1998-12-15

Family

ID=10761486

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95931282T ATE174139T1 (de) 1994-09-16 1995-09-08 Buszuweisungssystem für digitalsignalprozessoren

Country Status (14)

Country Link
EP (1) EP0781433B1 (Direct)
JP (1) JPH10505925A (Direct)
AT (1) ATE174139T1 (Direct)
AU (1) AU3477695A (Direct)
BR (1) BR9509071A (Direct)
DE (1) DE69506427T2 (Direct)
ES (1) ES2127554T3 (Direct)
FI (1) FI971093A7 (Direct)
GB (1) GB9418753D0 (Direct)
IL (1) IL115147A (Direct)
IN (1) IN184524B (Direct)
MX (1) MX9701974A (Direct)
WO (1) WO1996008774A1 (Direct)
ZA (1) ZA957740B (Direct)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2263951C2 (ru) * 2004-02-02 2005-11-10 Огородник Дмитрий Викторович Способ обработки цифровых данных в запоминающем устройстве и запоминающее устройство для осуществления способа
JP5130754B2 (ja) * 2007-03-15 2013-01-30 富士通セミコンダクター株式会社 半導体集積回路及びメモリシステム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837736A (en) * 1987-05-01 1989-06-06 Digital Equipment Corporation Backplane bus with default control
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
SE9203016L (sv) * 1992-10-14 1994-04-15 Ericsson Telefon Ab L M Signalbehandlingssystem med delat dataminne
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus

Also Published As

Publication number Publication date
FI971093L (fi) 1997-03-14
DE69506427D1 (de) 1999-01-14
ES2127554T3 (es) 1999-04-16
GB9418753D0 (en) 1994-11-02
AU3477695A (en) 1996-03-29
FI971093A0 (fi) 1997-03-14
WO1996008774A1 (en) 1996-03-21
EP0781433B1 (en) 1998-12-02
MX9701974A (es) 1998-02-28
JPH10505925A (ja) 1998-06-09
IN184524B (Direct) 2000-09-02
IL115147A (en) 1999-09-22
EP0781433A1 (en) 1997-07-02
BR9509071A (pt) 1997-12-23
DE69506427T2 (de) 1999-08-05
FI971093A7 (fi) 1997-03-14
ZA957740B (en) 1996-05-06
IL115147A0 (en) 1995-12-31

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties