ATE135833T1 - Speicherkonfiguration zur verwendung für schnittstellenbildung zwischen einer systemsteuereinheit für ein multiprozessorsystem und dem hauptspeicher - Google Patents
Speicherkonfiguration zur verwendung für schnittstellenbildung zwischen einer systemsteuereinheit für ein multiprozessorsystem und dem hauptspeicherInfo
- Publication number
- ATE135833T1 ATE135833T1 AT89309275T AT89309275T ATE135833T1 AT E135833 T1 ATE135833 T1 AT E135833T1 AT 89309275 T AT89309275 T AT 89309275T AT 89309275 T AT89309275 T AT 89309275T AT E135833 T1 ATE135833 T1 AT E135833T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- scu
- transfer
- segments
- cpus
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Multi Processors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Exchange Systems With Centralized Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/306,404 US5043874A (en) | 1989-02-03 | 1989-02-03 | Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE135833T1 true ATE135833T1 (de) | 1996-04-15 |
Family
ID=23185151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT89309275T ATE135833T1 (de) | 1989-02-03 | 1989-09-13 | Speicherkonfiguration zur verwendung für schnittstellenbildung zwischen einer systemsteuereinheit für ein multiprozessorsystem und dem hauptspeicher |
Country Status (7)
Country | Link |
---|---|
US (1) | US5043874A (de) |
EP (1) | EP0380855B1 (de) |
JP (1) | JPH02208771A (de) |
AT (1) | ATE135833T1 (de) |
AU (1) | AU628528B2 (de) |
CA (1) | CA1323929C (de) |
DE (1) | DE68926036T2 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6807609B1 (en) * | 1989-12-04 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system |
US5251310A (en) * | 1990-06-29 | 1993-10-05 | Digital Equipment Corporation | Method and apparatus for exchanging blocks of information between a cache memory and a main memory |
US5367642A (en) * | 1990-09-28 | 1994-11-22 | Massachusetts Institute Of Technology | System of express channels in an interconnection network that automatically bypasses local channel addressable nodes |
US5247643A (en) * | 1991-01-08 | 1993-09-21 | Ast Research, Inc. | Memory control circuit for optimizing copy back/line fill operation in a copy back cache system |
CA2065992A1 (en) * | 1991-06-07 | 1992-12-08 | Jorge Eduardo Lenta | Personal computer with enhanced memory access and method |
JP2672916B2 (ja) * | 1991-12-13 | 1997-11-05 | 富士通株式会社 | アレイディスク装置のデータチェック方法 |
GB2277181B (en) * | 1991-12-23 | 1995-12-13 | Intel Corp | Interleaved cache for multiple accesses per clock in a microprocessor |
US5265212A (en) * | 1992-04-01 | 1993-11-23 | Digital Equipment Corporation | Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types |
EP0613088A1 (de) * | 1993-02-24 | 1994-08-31 | Digital Equipment Corporation | Verfahren zur Speicherverschachtelung und dadurch verschachtelte Speichersysteme |
CA2118662C (en) * | 1993-03-22 | 1999-07-13 | Paul A. Santeler | Memory controller having all dram address and control signals provided synchronously from a single device |
US5377338A (en) * | 1993-10-12 | 1994-12-27 | Wang Laboratories, Inc. | Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency |
US5464435A (en) * | 1994-02-03 | 1995-11-07 | Medtronic, Inc. | Parallel processors in implantable medical device |
US5617534A (en) * | 1994-02-16 | 1997-04-01 | Intel Corporation | Interface protocol for testing of a cache memory |
US5696917A (en) * | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
TW304254B (de) | 1994-07-08 | 1997-05-01 | Hitachi Ltd | |
WO1996011440A1 (en) * | 1994-10-06 | 1996-04-18 | Virc, Inc. | Shared memory system |
US5590299A (en) * | 1994-10-28 | 1996-12-31 | Ast Research, Inc. | Multiprocessor system bus protocol for optimized accessing of interleaved storage modules |
US5596740A (en) * | 1995-01-26 | 1997-01-21 | Cyrix Corporation | Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks |
US5875470A (en) * | 1995-09-28 | 1999-02-23 | International Business Machines Corporation | Multi-port multiple-simultaneous-access DRAM chip |
US5663924A (en) * | 1995-12-14 | 1997-09-02 | International Business Machines Corporation | Boundary independent bit decode for a SDRAM |
US5761727A (en) * | 1996-04-02 | 1998-06-02 | United Microelectronics Corporation | Control apparatus for a memory architecture using dedicated and shared memory segments |
US6041379A (en) * | 1996-10-04 | 2000-03-21 | Northrop Grumman Corporation | Processor interface for a distributed memory addressing system |
US5946710A (en) * | 1996-11-14 | 1999-08-31 | Unisys Corporation | Selectable two-way, four-way double cache interleave scheme |
US5931938A (en) * | 1996-12-12 | 1999-08-03 | Sun Microsystems, Inc. | Multiprocessor computer having configurable hardware system domains |
US5960455A (en) * | 1996-12-30 | 1999-09-28 | Unisys Corporation | Scalable cross bar type storage controller |
US6216240B1 (en) * | 1997-06-26 | 2001-04-10 | Samsung Electronics Co., Ltd. | Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods |
US6012136A (en) * | 1997-12-01 | 2000-01-04 | Advanced Micro Devices, Inc. | Communications system with a configurable data transfer architecture |
US5872993A (en) * | 1997-12-01 | 1999-02-16 | Advanced Micro Devices, Inc. | Communications system with multiple, simultaneous accesses to a memory |
US6128307A (en) * | 1997-12-01 | 2000-10-03 | Advanced Micro Devices, Inc. | Programmable data flow processor for performing data transfers |
EP2357564A3 (de) * | 1998-02-04 | 2011-11-23 | Panasonic Corporation | Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm |
US6173367B1 (en) * | 1999-05-19 | 2001-01-09 | Ati Technologies, Inc. | Method and apparatus for accessing graphics cache memory |
EP1067461B1 (de) * | 1999-07-08 | 2013-04-24 | Texas Instruments France | Vereinheitlichtes Speicherverwaltungssystem für heterogene Multiprozessor-Architektur |
US7509391B1 (en) | 1999-11-23 | 2009-03-24 | Texas Instruments Incorporated | Unified memory management system for multi processor heterogeneous architecture |
US6748480B2 (en) * | 1999-12-27 | 2004-06-08 | Gregory V. Chudnovsky | Multi-bank, fault-tolerant, high-performance memory addressing system and method |
US6381669B1 (en) | 1999-12-27 | 2002-04-30 | Gregory V. Chudnovsky | Multi-bank, fault-tolerant, high-performance memory addressing system and method |
US6760743B1 (en) | 2000-01-04 | 2004-07-06 | International Business Machines Corporation | Instruction memory system for multi-processor environment and disjoint tasks |
US7788642B2 (en) * | 2005-05-16 | 2010-08-31 | Texas Instruments Incorporated | Displaying cache information using mark-up techniques |
JP4617282B2 (ja) * | 2006-08-31 | 2011-01-19 | 富士通株式会社 | 負荷発生装置及び負荷試験方法 |
US7908530B2 (en) * | 2009-03-16 | 2011-03-15 | Faraday Technology Corp. | Memory module and on-line build-in self-test method thereof for enhancing memory system reliability |
US8614920B2 (en) * | 2012-04-02 | 2013-12-24 | Winbond Electronics Corporation | Method and apparatus for logic read in flash memory |
US9595350B2 (en) * | 2012-11-05 | 2017-03-14 | Nxp Usa, Inc. | Hardware-based memory initialization |
US20140258780A1 (en) * | 2013-03-05 | 2014-09-11 | Micron Technology, Inc. | Memory controllers including test mode engines and methods for repair of memory over busses used during normal operation of the memory |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1394431A (en) * | 1971-06-24 | 1975-05-14 | Plessey Co Ltd | Multiprocessor data processing system |
US4037210A (en) * | 1973-08-30 | 1977-07-19 | Burroughs Corporation | Computer-peripheral interface |
US4207609A (en) * | 1978-05-08 | 1980-06-10 | International Business Machines Corporation | Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system |
US4449183A (en) * | 1979-07-09 | 1984-05-15 | Digital Equipment Corporation | Arbitration scheme for a multiported shared functional device for use in multiprocessing systems |
US4392200A (en) * | 1980-01-28 | 1983-07-05 | Digital Equipment Corporation | Cached multiprocessor system with pipeline timing |
US4371929A (en) * | 1980-05-05 | 1983-02-01 | Ibm Corporation | Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory |
US4500958A (en) * | 1982-04-21 | 1985-02-19 | Digital Equipment Corporation | Memory controller with data rotation arrangement |
US4543626A (en) * | 1982-12-06 | 1985-09-24 | Digital Equipment Corporation | Apparatus and method for controlling digital data processing system employing multiple processors |
US4543628A (en) * | 1983-01-28 | 1985-09-24 | Digital Equipment Corporation | Bus for data processing system with fault cycle operation |
CA1221464A (en) * | 1983-12-26 | 1987-05-05 | Hidehiko Nishida | Data processor system having improved data throughput of multiprocessor system |
US5067071A (en) * | 1985-02-27 | 1991-11-19 | Encore Computer Corporation | Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus |
JPS6289149A (ja) * | 1985-10-15 | 1987-04-23 | Agency Of Ind Science & Technol | 多ポ−トメモリシステム |
US4876643A (en) * | 1987-06-24 | 1989-10-24 | Kabushiki Kaisha Toshiba | Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests |
-
1989
- 1989-02-03 US US07/306,404 patent/US5043874A/en not_active Expired - Lifetime
- 1989-08-10 CA CA000607967A patent/CA1323929C/en not_active Expired - Fee Related
- 1989-09-13 DE DE68926036T patent/DE68926036T2/de not_active Expired - Fee Related
- 1989-09-13 EP EP89309275A patent/EP0380855B1/de not_active Expired - Lifetime
- 1989-09-13 AT AT89309275T patent/ATE135833T1/de not_active IP Right Cessation
- 1989-09-20 JP JP1244889A patent/JPH02208771A/ja active Pending
-
1990
- 1990-04-27 AU AU53942/90A patent/AU628528B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
US5043874A (en) | 1991-08-27 |
CA1323929C (en) | 1993-11-02 |
EP0380855A2 (de) | 1990-08-08 |
DE68926036T2 (de) | 1997-01-02 |
JPH02208771A (ja) | 1990-08-20 |
EP0380855B1 (de) | 1996-03-20 |
DE68926036D1 (de) | 1996-04-25 |
AU628528B2 (en) | 1992-09-17 |
EP0380855A3 (de) | 1991-02-06 |
AU5394290A (en) | 1991-12-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE135833T1 (de) | Speicherkonfiguration zur verwendung für schnittstellenbildung zwischen einer systemsteuereinheit für ein multiprozessorsystem und dem hauptspeicher | |
ES8609770A1 (es) | Una instalacion de control de acceso a memoria,de aplicaciona ordenadores | |
PH24161A (en) | Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization | |
DE3751853D1 (de) | Vorrichtung für ein fehlertolerantes Rechnersystem mit erweiterungsfähigem Prozessorabschnitt | |
SE8405456L (sv) | Mycket snabbt minnes- och minnesforvaltningssystem | |
EP0301921A3 (de) | Digitales Verarbeitungssystem | |
ATE188563T1 (de) | Mikroprozessorarchitektur mit der möglichkeit zur unterstützung mehrerer verschiedener prozessoren | |
US4691280A (en) | High performance multi-processor system | |
EP0389001A3 (de) | Mehrprozessorsteuerung für Vektorrechner | |
EP0261751A3 (de) | Simultanes Speicherzugriffssystem | |
JPS56123051A (en) | Data transfer system in master slave system | |
DE69033601T2 (de) | Multiprozessorsystem und Verfahren | |
JPS5730014A (en) | Input and output system | |
JPS6478361A (en) | Data processing system | |
DE3878044D1 (de) | Schaltungsanordnung zur steuerung von parallelzugriffen zu dezentralen speichereinrichtungen (fehleradressenspeicher). | |
SU1381533A1 (ru) | Процессор дл выполнени математических операций | |
SU881724A1 (ru) | Устройство дл ввода за вок от абонента в электронную вычислительную машину | |
JPS57197661A (en) | Multiplex controlling system for file memory | |
JPS57113166A (en) | Data processor | |
Boslaugh | Tactical Computer Standardization in the Navy. | |
JPS6468873A (en) | System control system | |
JPS5492145A (en) | Processing method for data on large-scale memory unit | |
JPS6476132A (en) | Inter-storage unit page data transfer control system | |
JPS6459445A (en) | Dma control system | |
JPS6468874A (en) | System control system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |