AT505507A1 - METHOD AND DEVICE FOR LIMITING THE INDUCTION IN THE CORE OF CHANGING TRANSFORMERS SWITCHED ON A DC VOLTAGE - Google Patents

Description

       

  Method and device for limiting the induction in the core of alternately switched to a DC voltage transformers. 
The invention relates to a method for controlling alternately switched to a DC voltage transformers, as described in the preamble of claim 1. 
The economic importance of push-pull converters or  Inverters switching a DC voltage alternately in the positive and negative direction to a transformer consists, in the main, that the power transformer, which significantly affects the cost price, theoretically can transmit twice as much power with the same size, because the core of the transformer in both Directions, rather than being magnetized in one direction only. 

   Practically, the advantage weighs rather heavier, because in the case of the forward converter, the magnetization achieved after a drive phase in the transformer does not completely degrade in the load case due to the commutation of the magnetizing current to the secondary side.  Therefore, the maximum duty cycle of the circuit breaker or  reduces maximum pulse width of theoretically half a period of the switching frequency, which is why the forward converter can be transmitted in a first approximation proportional to this reduction less power. 

   For push-pull converters, the maximum duty cycle is nearly 50%, somewhat less due to the finite switching speed of the circuit breaker. 
The utilization of this cost advantage is in many applications, however, the unsatisfactory solved saturation problem of the power transformer, due to its large main inductance LH and its low internal resistance R [tau] also taking into account the switch and diode, or  Valve flow voltages represents a very weakly damped integrating route. 

   If the positive impulses applied to the transformer by the push-pull structure are only slightly larger than the negative ones, or vice versa, then this fault is integrated, so that in particular in dynamically demanding applications the transformer suddenly saturates and becomes a short circuit, which becomes instantaneous Shutdown of the device or leads to its destruction. 
Now, the detection of incipient transformer saturation, such as by subtraction of the primary and secondary currents to be measured very expensive and would require high-precision Hall sensors required.  In any case, the detection of incipient saturation places high demands on the accuracy and speed of the measurement. 

   This problem also persists in half-bridge balanced converters, whose transformer is connected in series with a capacitive voltage center, ie with a capacitor, which compensates for steady state voltage equalization of unequal length positive and negative pulses on the transformer, because the transformer is sufficiently large difference in the duration of two successive positive and negative pulses, for example, causes a rapid change in the setpoint value of the output variable and thus the pulse widths corresponding to these output variables, before the center point voltage shifts. 

   Therefore, push-pull structures initially had mainly theoretical significance. 
The economic importance of push-pull converters has only begun to increase since 1990, due to the availability of modern, robust, comparable nearly powerless controllable power semiconductors, such as FET or IGBT, with sufficiently constant, jitter-free switching delay and driver cycle times and driver circuits equipped with a sufficiently fast overcurrent shutdown are. 
Nevertheless, the range of application remained limited until 1993 to applications with low dynamic requirements, because the alternately positive and negative pulses on the power transformer may change only slowly with respect to the switching frequency, in order to prevent the danger of a steady magnetization and saturation of the transformer. 

   If, starting from a certain positive or negative pulse, the pulse width of the following impulses is significantly larger or smaller compared to the past, then the resulting power magnetization magnetization degrades only very slowly, in terms of order of magnitude, with the time constant TH = LH / R [iota] ,  In the meantime even smaller pulse changes can lead to immediate saturation. 
In order to come closer to the theoretically achievable dynamics associated with the switching frequency, it is currently also possible to connect the power transformer in series with a pulse-resistant capacitor of small capacitance.  In the case of the half-bridge inverter, the supporting capacitors can be selected to be correspondingly small so that it is no longer possible to assume a fixed center-point voltage. 

   Although a direct magnetization is then compensated faster, but the voltage across the power transformer is reduced by the capacitive voltage drop, so the less power can be transmitted, the more dynamically the inverter is designed.  Due to the capacitive voltage loss, less power can be transmitted. 

   At the same time, the power transformer must be oversized to withstand the transient DC magnetization until the voltage on the coupling capacitor degrades the DC magnetization. 
The full bridge with phase shift control is so far a special push-pull converter, because the magnetization of the transformer takes place exclusively at the same time as the power transmission and its magnetization in the intervening pauses - the so-called free-wheeling intervals - remains almost undiminished. 
- 2 Practical experiences with the full bridge with
Phase shift control and already available modern drivers and circuit breakers have shown that it is sufficient to generate sufficiently accurate control pulses,

   due to theoretically - presumptive assumption - exceeding of the maximum permissible magnetization of the
Power transformer does not occur.  This effect is achieved by the fact that from the setpoint voltage or  Controller output voltage those frequency components are filtered out, which would cause a steady increase in the magnetization, which can be dispensed with a direct saturation detection at the transformer in favor of a cost prefilter between controller output and pulse width modulator input. 

   According to the published patent specification of the German Patent Office DE 196 34 713 AI even methods that allow for the occurrence of periodic setpoint changes stationary steady magnetization, the decay of the same is not taken into account. 
In the published patent application methods are shown in which initially exactly half the pulse width change is passed, so theoretically the maximum magnetization is not exceeded, depending on the amount of a periodic setpoint fluctuation can occur a DC magnetization. 

   The methods have proven to be practical and led to a significant increase in the dynamic properties of the full bridge, without the transferable power reducing coupling capacitor and without oversizing of the power transformer, the core, however, must be designed for the largest operating voltage. 
However, the methods presented therein still reduce the achievable dynamics of the power unit because, according to the method, half the setpoint change from the power unit must always be processed first.  The achievable dynamics of such a full bridge is therefore comparable to that achieved with two by 180 °. ] offset working forward converters that operate at half the switching frequency, can be achieved. 

   Furthermore, the old setpoint must be stored in order to calculate the pulse width to be output according to the formula Us = (US / a [iota] t + Us, neu) / 2, which is why only a digital realization makes sense due to the required accuracy. 
In conventional PWM control of the full bridge, and also, for example, in the case of a half-bridge balanced transformer, a load-dependent demagnetization interval takes place after the end of a power-transmitting period in which the remaining magnetizing current commutates to the secondary side.  In the case of high dynamic inverter requirements, it may therefore be necessary to perform a feedback operation, while the full bridge with phase shift control could already be upgraded to high dynamic requirements, at least with the pre-filter procedure without feedback. 

   In any case, the inventive approach with feedback of the transformer voltage also ensures the protection of the transformer at a higher and fluctuating supply voltage, which is naturally not given in the pre-filter.  For example, in applications in the railway supply network, where must be expected with a wide range fluctuating supply voltage, the prefilter method is unsuitable because the transformer current for the minimum operating voltage, the core of the transformer, however, to the maximum operating voltage, the transformer for a much greater performance would have to be interpreted

   whereas, in accordance with the invention, the transformer core can advantageously also be designed only for the minimum operating voltage, and the transformer can be designed for the rated power of the device. 
The present invention has for its object to expand the scope of Gegentaktstrukturen and fully usable without sacrificing the reliability of their dynamic resources. 
The object of the invention is achieved by the method according to claims 1 to 9 and by the devices according to claims 10 to 14. 
Advantageously, in the method according to claim 1, the detection of the non-linear transformer saturation is unnecessary, and in contrast to the known methods, it is advantageous not only for the controller output but for the output of the pulse width modulator in the case of imminent saturation of the transformer

  intervened.  As a result, the theoretically achievable dynamics of the inverter is again significantly increased.  In addition, the procedure of claim 2 is possible because the transformer is operated in the linear range. 
In the procedure according to claim 2, the magnetization of the transformer is determined inexpensively by integration of a signal whose course corresponds to that of the transformer primary voltage. 
In the procedure according to claim 3, a magnetic voltage converter can be used cost-effectively, which is also operated in the linear range.  Furthermore, fluctuating switching delay times are taken into account, which is why it is particularly advantageous not only to use cost-effective pulse width modulators, but also cost-effective driver circuits. 

   Furthermore, any demagnetizing intervals that may occur, as well as parasitic effects, such as the balancing effect parasitic switch capacitances and the reduction of the transformer voltage to the forward voltages of the current-carrying valves and the voltage drops across the parasitic resistors and thus also the decreasing tendency of any existing DC magnetization with reduced pulse width Thus, the method can be advantageously applied to all push-pull structures. 

   In any case, the inverter can already be economically operated on variable supply voltage, because the transformer must be dimensioned only for a corresponding to the fluctuation of the supply voltage above the rated power of the device lying power, for example, to 120% of the rated power for supply voltage fluctuations of + -10%. 
By the procedure of claim 4 or 5 is advantageously achieved that the transformer core can be designed for the lower limit of the intermediate circuit voltage. 

   The procedure of claim 4 is particularly suitable for digital implementation, while the procedure of claim 5 in a similar manner is particularly simple. 
The procedure of claim 6 is useful, with only slightly fluctuating supply voltage of the inverter, z. B.  + -10% and especially for the phase-shift-controlled full-bridge inverter.  Advantageously, no feedback and thus no voltage converter is needed.  Inexpensive, the transformer magnetization is obtained by integration of a signal derived directly from the control signals. 

   It is also advantageous to use a cost-effective pulse width modulator. 
In the procedure according to claim 7, the decay of the direct magnetization is cost-effectively taken into account in the unlikely event that longer quasi-stationary states are terminated or interrupted by rapid setpoint changes. 
The procedure of claim 8 is advantageous if it is essentially a linear demagnetization of the transformer against the sum of the lying in the freewheel circle valve voltages. 

   This can also be realized inexpensively by means of a digital counter. 
The procedure of claim 9 is advantageous if an exponential decay in the freewheeling phases or  an exponentially decreasing increase in the magnetization is determined by the internal resistance in the respective circuit for the demagnetization of the transformer.  When executed in conventional analog technology, the possibly determining attenuation by the parasitic resistors can be easily and inexpensively by parallel connection of a correspondingly high-impedance resistor to the integration capacitor taken into account. 

   This procedure is already feasible in digital technology at low cost. 
In the procedure according to one or more of claims 7 to 9, the power transformer can be advantageously designed for the maximum operating voltage. 
Claim 10 describes a device 40 which can be used for all push-pull converters and variable supply voltage. 

   Claim 11 describes a device 40 according to claim 10, wherein the transformer is utilized as well as possible. 
The method according to claim 12 advantageously reduces the over-dimensioning of the transformer beyond the required nominal power of the device, in particular in applications for a wide supply voltage range. 
The procedure according to claim 13 advantageously eliminates the need to define two further values for limiting the amplitude of the fed-back transformer voltage. 
The procedure of claim 14 represents a cost-effective implementation of claim 12. 
By the procedure of claim 15, the required over-dimensioning of the transformer is avoided in particular due to a fluctuating supply voltage. 
Claim 16 describes a principle for all push-pull converters in application areas,

   where an approximately constant supply voltage is present, suitable device 50, the cost without the detection of
Transformer primary voltage gets by. 
The procedure of claim 17 makes it possible to interpret the core of the transformer not far above that magnetic flux, as that which can occur in steady state operation at the maximum supply voltage. 
The procedure according to claims 17, 18 and 19 allows a further reduction of the core cross-section of the transformer, or 

   finally, its design for operation at the maximum supply voltage, even in the unlikely event that the application process requires rapid changes in the output, which are interrupted by longer quasi-stationary operating conditions. 
For a better understanding of the invention, this will be described in more detail below with reference to the half-bridge and full-bridge converter. 
Show it;
FIG. 1: the block diagram of the half-bridge inverter;
FIG. 2: the block diagram of the full-bridge inverter with phase-shift control;
FIG. 3:

   Process diagram of a power electronic DC-DC converter according to DE 196 34 713 A 1;
FIG. 4: one of an inverter, which is controlled by a primary side feedback correction circuit, alternately connected to a DC voltage transformer with secondary rectifier connected and connected to this rectifier loads or  the process diagram for claim 1;
FIG. 5: Block diagram of
Induction limiting device;
FIG. 6: Circuit diagram for integrator and
Induction limiting device for the half-bridge differential converter;
FIG. 7: Time courses of control signals, resulting
Transformer voltage and transformer magnetization for the half-bridge inverter in FIG. 1 with induction limiting according to the invention according to FIG. 6;
FIG. 8th:

   Magnetization curves at maximum pulse width for different supply voltages;
FIG. 9: Circuit extension for the integrator circuit in FIG. 6 for consideration of a variable supply voltage;
FIG. 10: Time courses of control signals, resulting
Transformer voltage and transformer magnetization for the full-bridge inverter with phase shift control in FIG. 2 with induction limiter according to the invention according to FIG. 6 with logic circuit of FIG. 11;
FIG. 11: Circuit diagram for an exemplary logic circuit for the full-bridge inverter with phase shift control in FIG. 2;
FIG. 12: the process diagram for a non-feedback procedure;
FIG. 13:

   Circuit example for integrator and a non-feedback induction limiting device for the half-bridge converter in FIG. 1;
FIG. 14: exemplary extended integrator circuit for the full bridge inverter with
Phase shift control taking into account the transformer demagnetization tendency;
FIG. FIG. 15 shows time profiles of the essential variables during a period of the switching frequency of the inverter in FIG. 2 for explaining the circuit in FIG. 14th 
FIG. 1 shows the inverter 13 whose supply lines 1 and 2 are connected to the output of a voltage intermediate circuit, for example to the capacitor at the output of a mains rectifier. 

   To the lines 1 and 2 two connected by line 3 in series capacitors or voltage sources 27 and 28 are connected so that the voltage difference between line 1 and line 3, as well as between the lines 3 and 2 is half the DC link voltage.  The positive power connections of switch 8 and the diode 9 are connected to line 1, the negative power connections to line 4.  The positive power connections of switch 11 and diode 12 are connected to line 4, the negative power connections to line 2.  The control line 5 is connected to the input of the driver circuit 7, whose output is connected to the control input of the switch 8. 

   The control line 6 is connected to the input of the driver circuit 10, whose output is connected to the control input of the switch 11. 
In the driver circuits 7 and 10 is also the
Switch-on delay time built-in when the circuit breakers have about a greater off-delay, so that it can come at full scale - the switch-on on control line 5 comes simultaneously with the switch-off on control line 6 and vice versa - no bridge short circuit. 
Between the lines 4 and 3 is the
Output AC voltage 29, which is positively equal to half the DC link voltage when switch 8 is closed, is half the negative DC link voltage as long as switch 11 is closed, and is predominantly zero,

   when both switches are open. 
In Fig. 2 is the basic circuit of a
Full-bridge inverter with phase shift control shown.  The positive terminals of the switches 14 and 20, as well as the diodes 15 and 21 are connected to line 1.  The negative terminals of the switches 17 and 23 and the diodes 18 and 24 are connected to line 2.  The positively counted output of the inverter is line 4, to which the negative terminals of switch 14 and diode 15 and the positive terminals of switch 17 and diode 18 are connected.  The negatively counted output of the inverter forms line 3 which connects the negative terminals of switch 20 and diode 21 and the positive terminals of switch 23 and diode 24. 

   The output AC voltage 29 is applied between the lines 4 and 3. 
The control input of switch 14 is connected to the output of driver circuit 16.  At the input of the driver circuit 16, the control line 5 is connected.  Switch 17 is driven by driver 19.  The input of the driver 19 is connected to the output of an inverter 51 whose input is also connected to line 5.  The control input of switch 20 is connected to the output of driver circuit 22.  At the input of the driver circuit 22, the control line 6 is connected.  Switch 23 is driven by driver 25.  The input of the driver 25 is connected to the output of the inverter 52, whose input is also connected to line 6. 
The signals on the control lines 5 and 6 are square-wave voltages with a duty cycle of 50% in the steady state. 

   The necessary switch-on delay is realized in the driver circuits.  The signal on the control line 5 leads the signal on control line 6 ahead.  The signal on line 5 controls the leading bridge branch 14, 17 and the signal on line 6 controls the trailing bridge branch 20, 23. 
The circuit breakers 14, 17, 20, 23, the diodes 15, 18, 21, 24 are connected in anti-parallel because the common circuit breaker in the on state can only lead in the direction of positive to negative power connection current. 
By closing the switches 14 and 23, the positive DC link voltage is applied to the output, by closing the switches 17 and 20, the negative. 

   The width of the positive and negative pulses of the output AC voltage 29 results from the phase shift of the signals 5 and 6, as well as the duration of the intermediate freewheeling phases switch 14 and 20 or switches 17 and 23 are closed or  open. 
FIG. 3 shows the method steps in the DC-DC conversion according to the method described in the published patent application DE 196 34 713 AI.  The power rectifier 32 is connected to the input side of the network 31, its positive output is connected to line 1 and its negative output to line 2.  The DC link capacitor is on the one hand connected to line 1, on the other hand connected to line 2.  Line 1 and 2 are the supply lines of the inverter 26, at the output, formed by the lines 4 and 3, the primary side of the power transformer 30 is connected. 

   The pulse widths of the output AC voltage 29 is determined by the signals on the control lines 5 and 6.  The secondary side of the transformer 30 is connected to the input of the secondary rectifier 33, at whose output the load 34 is connected. 
The load voltage is detected by the voltage measuring device 35 and supplied to the controller 41 with the lines 36.  On line 38, the controller 41 receives the actual value of the load current.  The controller 41 compares the current actual value on line 38 with the current setpoint on line 39 or the load voltage on line 36 with the voltage setpoint on line 40 and regulates with its output voltage on line 42 corresponding to a certain pulse width of the positive and negative pulses on transformer 30. the power flow. 

   The controller 41 is connected on the output side by line 42 to the input of the pre-filter 83, whose output is connected via line 82 to the input of the pulse width modulator 43.  At the output of the pulse width modulator 43, the control lines 5 and 6 of the inverter 26 are connected. 
In the current state of the art, the pre-filter 83 applies to its output on line 82 a value corresponding to only a part of the change at its input to line 42, so that the pulse width modulator 43 generates control signals 5 and 6 for the inverter such that at arbitrary Changes to the controller output on line 42 of the power transformer is not expected to saturate, or  a maximum permissible transformer magnetization is not exceeded. 

   The pre-filter 83 thus fulfills its function of filtering out the harmonic and subharmonic oscillations of the switching frequency of the inverter possibly contained in the desired value signal 42, which would lead to a steady increase in the transformer DC magnetization.  Without pre-filter 83 and without further measures to prevent dangerously recurrent setpoint changes, eg. B.  By reducing the system dynamics, for example by means of the pre-filtering method discussed, the dangerous transformer short-circuit due to the saturation of its core, even with a significantly oversized transformer would only just adjust a little later. 
In FIG. 4, compared with the prior art in FIG. 

   3, the control lines 5 and 6 are fired at the output of the device 40 operating according to the method according to the invention, whose signal inputs are connected via the lines 45 and 46 to the outputs of the pulse width modulator 43.  Two further inputs of the device 40 are connected via the lines 47 and 48 to the secondary side of the voltage converter 49, whose primary side is connected to the output lines 3 and 4 of the inverter 13. 
FIG.  5 shows the block diagram of the device 40. 

   This consists of the integrator 73, a circuit part which defines the critical values of the transformer magnetization in the positive and negative directions on the lines 55 and 56, the comparators 63, 64 and a logic circuit 78 or 79th 
The feedback transformer voltage 72 is supplied with the lines 47 and 48 to the input of the integrator 73.  Line 62 connects the output of integrator 73 to the negative input of comparator 63 and to the positive input of comparator 64.  The positive input of comparator 63 is connected to line 55 at which the positive critical value of the magnetizing current is tapped. 

   The also fixed potential on line 56, which is connected to the negative input of the comparator 64, determines the negative critical value of the transformer magnetization. 
Line 80 from the output of the comparator 63, line 81 from the output of the comparator 64, as well as the lines 45 and 46 from the outputs of the pulse width modulator 43 are connected to the inputs of a logic circuit 78 or 79, the control signals 45 and 46 to their outputs to the Lines 5, and 6 turns on as long as the voltages on lines 80 and 81 indicate that the magnetization of transformer 30 is within the allowable limits set on lines 55 and 56. 

   Logic circuit 78 or  79 directs the signals 45 and 46 of the pulse width modulator 43, which are predetermined due to the load of the transformer 30 by the application process, unchanged on the control lines 5 and 6 of the inverter 13 or 26, the alternating DC voltage alternately determined by the application process time in positive and negative direction to the primary winding of transformer 30, unless that is removable on line 62, of integrator 73 of the magnetization of transformer 30 or 

   of the parallel-connected voltage converter 49 magnetized signal has reached the critical value in the positive or negative direction. 
In the case of the inverter 13, logic circuit 78 outputs a correspondingly shortened control pulse to the control pulse on line 45 on line 5 when the magnetization signal reaches the positive critical value on line 55 and the comparator 63 has responded.  The control pulse on line 46 on line 6 is truncated when comparator 64 determines that the magnetization signal from transformer 30 has reached its negative critical value set on line 56. 
When Vollbrückenkonverter the capacitors 27, 28 are also replaced by circuit breakers. 

   In conventional PWM control, the switch built in instead of the capacitor 27 is switched on and off at the same time as the switch 11 and the switch at the location of the capacitor 28 is actuated together with the switch 8.  Unlike the half-bridge inverter, when the switch pair is switched through, the full intermediate circuit voltage is now applied to the transformer 30 in the positive or negative direction.  Again, logic circuit 78 can be used unchanged. 
In Fig. 9 is an example of a logic circuit 79 for the full-bridge inverter with phase-shift control 26 in FIG. 2 shown. 

   The logic circuit 78 is shown in FIG. 6 included. 
FIG.  FIG. 6 shows an exemplary embodiment of the device 40 operating according to method claim 1 with a logic circuit 78 for the half-bridge balanced converter and the full-bridge balanced converter with PWM control. 
Device 40 is powered by voltage 74, for example at 15 volts.  The magnetization limits, as well as the reference potential for the magnetization signal are determined by means of the series connection of the same size resistors 221, 54 with the Zener diodes 222, 53. 
Resistor 221 is connected to the positive electronics supply 74.  Line 55 connects its second terminal to the input of zener diode 222 and the positive differential input of comparator 63. 

   Line 57 connects the output of Zener diode 222 to the input of Zener diode 53 and the positive differential input of operational amplifier 71.  Line 56 connects the output of Zener diode 53 to resistor 54 and the negative differential input of comparator 64.  The second terminal of the resistor 54 is connected to the electronic ground 77.  The zener voltage of the diodes 222 and 53 is for example 1.8 volts.  Operational amplifier 71 buffers the zero potential for the magnetization signal present on line 48. 

   The potential of line 55 is z. B.  1.8 volts above the reference potential of line 48, the potential on line 56 is 1.8 volts below. 
Integrator 73 is exemplified as a inverting integrator consisting of operational amplifier 61, resistor 58 and capacitor 59, at whose input the voltage 72, which is proportional to the negative voltage to transformer 30, is fed back, so that the voltage at the integrator output the actual course of the magnetization in Transformer 30 follows. 
The positive terminal of the primary side of the voltage converter 49 is connected to line 4, the negative primary terminal is connected to line 3, so that at the primary side of the voltage converter 49, the inverter output voltage or  the primary voltage of the power transformer 30 is applied. 

   Voltage converter 49 is coupled so that a 29 in positive counting direction primary voltage pulse, based on the potential of line 48, a negative in the counting direction 72 voltage pulse at the integrator input on line 47. 
On line 48, the positive terminal of the secondary side of the voltage converter 49, the output and the negative differential input of the operational amplifier 71, and the positive differential input of the operational amplifier 61 are connected.  Line 47 connects the negative terminal of the secondary side of the voltage converter 49 with resistor 58, the further terminal of line 60 is connected to a terminal of the integration capacitor 59 and the negative differential input of the operational amplifier 61. 

   The second terminal of the capacitor 59 is connected to line 62, which is supplied by the output of the operational amplifier 61.  The formed at the output of the operational amplifier 61
Magnetization signal is further supplied from line 62 to the negative differential input of the comparator 63 and the positive differential input of the comparator 64. 
By virtue of voltage 72, a current flows through resistor 58 and on through capacitor 59, so that there is a voltage on line 62 which is equal to the integral of voltage 72 multiplied by -1, resp.  the course of the temporal integral of the transformer voltage 29 follows.  The outputs of the comparators 63, 64 are HIGH as the voltage on line 62 moves within the limits defined by lines 55, 56. 

   When the potential on line 55 is exceeded, comparator 63 responds and the signal on line 80 goes low.  If the potential on line 56 is undershot when a negative pulse to transformer 30 is applied, comparator 64 generates a LOW signal on line 81. 
The signals on the lines 80, 81 and the control signals on the lines 45, 46 are supplied to the logic circuit 78, at whose outputs the control lines 5, 6 are connected for the switches 8 and 11.  The logic circuit 78 is comprised of the inverters 67, 68, the negative edge-triggered RS flip-flops 65, 66, and two AND gates 69, 70. 
The reset input of flip-flop 65 is connected via line 80 to the output of the comparator 63.  The output of the FF 65 is connected via line 75 to an input of the AND gate 69, whose second input is connected to line 45. 

   The input of flip-flop 65 is connected to the output of the signal inverter 67 whose input is connected to line 46. 
The reset input of flip-flop 66 is connected via line 81 to the output of comparator 64, its input to the output of signal inverter 68 and its output via line 76 to an input of AND gate 70 whose second input is connected to line 46.  The input of the inverter 68 is connected to line 45. 
The lines 45 and 46 are connected to the outputs of the pulse width modulator 43. 

   The pulse width modulator 43 generates from the set point 42 required by the application process the signal 45 for the upper switch 8 which determines the positive pulse duration at the power transformer 30 and the signal 46 for the lower switch 11 of the inverter 13 (FIG. 1), which determines the negative pulse duration at the power transformer 30. 
During the turn-on state of switch 8 (FIG. 11), the control signal on line 45 (46) may be responsive to comparator 63 (64).  In this case, flip-flop 65 (66) is reset, line 75 (76) goes low, and AND gate 69 (70) takes the voltage signal from control line 5 (6), thereby interrupting current flow through switch 8 (11) positive (negative) voltage pulse to transformer 30 is terminated prematurely.  The reset pulse on line 80 (81) may be very short. 

   However, the output of flip-flop 65 (66) connected to line 75 (76) remains LOW until flip-flop 65 (66) is reset.  This is done only by the following switch-on command for switch 11 (8) on line 46 (45), whereby the premature restart of switch 8 (11) is reliably prevented. 
The voltage divider 221, 222, 53, 54 generates the upper integration limit on line 55, the
Bottom of integration on line 56 and the mid-lying potential on line 57, which is buffered by operational amplifier 71 and pending on line 48.  Resistor 58, capacitor 59 and operational amplifier 61 form the inverting integrator 73, which integrates the voltage 72, an image of the inverted transformer voltage 29. 

   When the output on line 62 moves within the limits imposed by lines 55 and 56, the outputs of comparators 63 and 64 are high.  The outputs of the flip-flops 65 and 66 are then also HIGH, especially as they are constantly running through the positive edges or  Enable commands of the control signals 45 and 46 are set.  In this case, the control signal 45 appears unchanged at the output of the AND gate 69 on line 5 and the control signal 46 unchanged at the output of the AND gate 70 which is connected to line 6. 
The comparator 63 responds or  its output becomes LOW when a positive pulse or  On command on line 45 is too long, and comparator 64 can only with a negative pulse of the transformer voltage 29 and  during the switch-on command on line 46. 

   Due to the demagnetization phase following each switch - off process in the inverter, see Fig. 7, the output pulses of the comparators 63 and 64 are very short, so they are extended by means of the RS flip-flops 65 and 66 until the turn-on of the other switch.  If comparator 63 responds, flip-flop 65 is reset and its output connected to line 75 goes low, whereby AND gate 69 removes turn-on signal 45 from line 5. 

   If comparator 64 responds, then the turn-on signal of line 46 at the output of AND gate 70 on line 6 is taken back via line 76. 
In Fig.  7, the function of the half-bridge inverter 13 in FIG. 1 with inventive control and logic circuit of FIG. 6 represented by the diagrams 84 to 92. 
Diagram 84 shows the mode of operation of the pulse width modulator 43, which, for example, measures two by 180 [deg. ] offset ramp signals 93 and 94 generated. 

   Furthermore, in plot 84, the setpoint voltage 95 is plotted on its input line 42, which is determined by the process in the region of application of the inverter 13. 
From the diagrams 85 and 86, the control signals on the lines 45 and 46 with the switching states 96 and 97 of the switches 8 and 11 can be seen, wherein the diagram 85, the switch states 96, 97 of the switch 8 and diagram 86, the switch states 96, 97 of the switch 11 represents. 
In diagram 87, the voltage 29 of the lines 4 and 3 connected to the primary winding of the transformer 30 is shown and in diagram 88, the time course 98 of the magnetization of the transformer 30 and 

   of the magnetization signal on line 62. 
When the inverter 13 is put into operation, the modulator 43 generates from the regulator output voltage 95 the control signal for the switch 8 which constitutes the device 40 according to the invention in FIG. 6 switches from line 45 to line 5 when voltage 98, and thus the magnetic flux in the transformer core, is within the specified limits.  Similarly, device 40 forwards the switch states 96, 97 for switch 11 of line 46 on line 6.  If the switch-on command on line 5 closes switch 8, the voltage of capacitor 27 is in the positive counting direction of voltage 29 at the primary winding of transformer 30.  When switch 11 is closed, the voltage of capacitor 28 is in the negative counting direction on the primary side of the power transformer. 

   The capacitors 27, 28 charge during commissioning to half the DC link voltage, which is present between the lines 1 and 2. 
Due to the alternate switching of the switches 8, 11, the primary voltage 29 is applied to the primary side of the transformer 30, which is transmitted and then z. B.  is rectified again via the secondary rectifier 33 and supplies the load 34 with power and voltage. 
As can be seen from the diagrams 85, 86, modulator 43 sets the switch-on time of switch 8 with the start of the ramp signal 93 and the switch-on time of switch 11 with the start of the ramp signal 94.  The switch-off time for switch 8 determines modulator 43 at equal voltage of ramp signal 93 and regulator output voltage 95, the switch-off for switch 11 is given at voltage equality of the signals 94 and 95. 

   In this way, modulator 43 determines the turn-on durations 99 for switches 8 and the turn-on durations 100 for switches 11. 
At the zero voltage point of the ramp signal 93 at a time
101, modulator 43 drives switch 8, thereby delaying transformer and switch cycle times to transformer 30, as shown in Chart 87, at the time
102 a in the counting direction of voltage 29 positive voltage corresponding to half the intermediate circuit voltage is placed. 

   At time 103, voltage equality occurs between ramp signal 93 and regulator output voltage 95, whereby modulator 43 takes the voltage signal from control line 45 and, somewhat delayed at time 104, the current flow through switch 8 is interrupted. 
As can be seen from the synopsis of the diagrams 87, 88, by applying a voltage to the transformer 30, its core is magnetized, i. H.  It forms through the primary winding of transformer 30 from a magnetizing current, the voltage proportional linear increase or  decreases.  The storage of the magnetizing current, or  Intervals in which the transformer voltage is zero can only occur if a load current has already formed.  The load is switched on at a later time 108 and inverters or 

   Transformer 30 are initially idle. 
By applying a positive voltage to the transformer 30, d. H.  the switch 8 is in the conductive state, from the time 102, the level of the nagative magnetization of the transformer 30 during the application of the positive voltage according to a linear function is reduced or  also reversed.  At time 104, the magnetizing current in the primary winding of transformer 30 due to the previously controlled switch 8, the amplitude 105. 

   Of the
Magnetizing current, which was previously fed by capacitor 27, commutates during the shutdown of switch 8 in the
Diode 12, causing capacitor 28 of the primary side of the
Transformers 30 is connected in antiparallel and
Transformer 30 against the voltage across capacitor 28, which corresponds to half the DC link voltage, demagnetized, d. H.  the negative voltage is at the transformer 30 until the
Magnetization current linear up to the value zero, which leads to a
Time reaches 108, has decreased. 
At the zero voltage point of the ramp signal 94 at a time 106 modulator 43 controls the switch 11, whereby the
In any case, transformer 30 delays the driver and switch cycle times in a negative voltage in the counting direction of voltage 29 1 1, which is half the intermediate circuit voltage, <*> '..' <*> matches.

   At time 107 occurs <*> .... *
Voltage equality between ramp signal 94 and; ;;
Regulator output voltage 95, whereby modulator 43, as shown in FIG <*> .. <*> '.
Diagram 86, the voltage signal from the ... '.
Control line 46 increases and slightly delayed, the flow of current through the switch 11, if present, is interrupted. [Iota] ... I.
As can be seen from graphs 87 and 88, the results in FIG. <>. *. Case illustrated the duration of the negative voltage pulse <*> <*> <*> Transformer 30 due to the magnetizing current 98 through diode 12th
At time 108, the transformer 30 is demagnetized, voltage 29 breaks down to the value zero and diode 12 appears a reverse voltage, which is half
DC link voltage corresponds.

   After time 108 and before time 109, the load 34 is now switched on.
At time 109, the pulse width modulator 43 on line 45 outputs an on state 97 for switch 8, which turns on at time 110 and applies half the intermediate circuit voltage in the positive direction to the transformer 30. Modulator 43 only takes the switch-on state 97 for switch 8 back to time 114, but the maximum permissible magnetization is already reached at time 111. The output of comparator 63 becomes LOW, as a result of which the output of flip-flop 65 is also connected to line 75.
The magnetization increases until time 112, in which switch 8 actually turns off, and the current in diode 12 still increments by B55 * 4 * tv / T over the line 55 set limit to the actual maximum positive magnetization with amplitude 116 that occurs.

   Calculated for tvjene use maximum time that can elapse between the turn-off time 111 of the control signal and the actual switching off switch 8 at time 112.
As a result of the voltage at the transformer 30, which is now negative from time 112, the current transmitted to the secondary side decreases rapidly to zero in accordance with a linear function whose slope is determined by the leakage inductance of transformer 30. On the secondary side, the load current is now no longer supplied by the primary side, but is driven by the inductive load and / or a series-connected to the load smoothing inductance, whereby the secondary rectifier is short-circuited.

   Therefore, another commutation of the
Magnetizing current to the secondary side, which is completed just after the start of the time interval 112, 113, when the magnetizing current makes up only a fraction of the load current. In Zeitindervall 112, 113 occurs due to the negative voltage 29, a partial demagnetization of transformer 30. If the leakage inductance of transformer 30, which was charged up to the time 112 to the load current, demagnetized at time 113 and diode 12 is no longer current flowing breaks the Transformer voltage together.

   The remaining magnetization at the value 117 stores transformer 30 on the secondary side.
As can be seen from graph 88, the voltage on line 62 drops below the value on line 55 in time interval 112, 113, and therefore the LOW pulse of comparator 63 must be extended.
Diagram 89 shows the output signal of flip-flop 65 on line 75. Flip-flop 65 is reset by the falling edge of the LOW pulse on line 80 and only at turn-on time 115 by the control signal on line 46 for switch 11, ie until the end of the maximum pulse width of switch 8 , again set.
Diagram 90 shows the control signal for switch 8.
The switching state is identical in the time interval 101, 111 with the control signal on line 45 in diagram 85.

   From time 111, it is taken from line 5 due to the signal on line 75 until the end of the theoretically possible maximum duty cycle at time 115.
A delay time after time 115, switch 11 becomes conductive. Modulator 43 outputs a large duty cycle, at the end of which the magnetization in diagram 88 has the negative amplitude 119 at the end after a further delay time until switch 11 is switched off at instant 118.

   Due to the change from set point signal 95, modulator 43 outputs a small duty cycle to transformer 30 for the now following positive pulse, so that transformer 30 already switches to negative at time 120 in which modulator 43 turns on switch 11 and applies a negative voltage pulse to transformer 30 Value 121 is biased and in this state does not tolerate a long negative [Xi] voltage pulse. After switching through switch 11 to time 122, the magnetization of transformer 30 continues to increase in the negative direction, so that already at time 122, the negative magnetization limit set on line 56 is reached, comparator 64 responds and flip-flop 66 resets.
Diagram 91 shows the output of flip-flop 66 on line 76, and in Diagram 92 the control signal for switch 11 on line 6 is shown.

   Flip-flop 66 is set only by the subsequent turn-on command for switch 8 at time 123, whereby the control signal for switch 11 at the time
122 is taken from the control line 6 until the end of the maximum duty cycle at time 123.
The switching states of the switches 8, 11 before and after the time intervals 112, 115 and 122, 123 correspond to their control signals generated by the modulator 43 on the lines 45, 46th

   In the period between the times 111 and 115 or 122
123, the control signals on lines 45 and 46 are taken from lines 5 and 6, respectively, so that the magnetization of transformer 30 is the maximum value in the positive direction set by the voltage on line 55 and the maximum value in the negative direction, respectively , which is determined by the voltage on line 56 does not exceed.
The signal curve in diagram 88 corresponds to the integrator output voltage on line 62 and the course of the induction B or of the magnetic flux [Phi] in the transformer core to which the magnetizing current is proportional.

   For the dimensioning of the transformer core, its maximum allowable induction BA is definite, which is determined by the induction value B55, which corresponds to the voltage on line 55.
8 shows the mutually corresponding curves of transformer magnetization and magnetization signal for a transformer connected to inverter 13 or 26 between times 110 and 112 for a minimum operating voltage UZK, MIN, ramp 150 and curve 151 at, for example, twice the operating voltage UZK, MAX = 2 * UZK, MIN, when using device 40 in Figure 6 with logic circuit 78 or 79, and a dash-dotted registered corrected course 159 of the magnetization signal, so that the maximum core induction is not exceeded at twice the operating voltage.
The estimated states on the control lines 5,

  6 occur later by the delay time tv as positive or negative pulse of the transformer primary voltage 29. The integration speed or voltage increase on line 62 results from the current with which capacitor 59 is CIN or discharged and is to be set by means of resistor 58 R [iota] NTso that during the maximum pulse width of the positive and negative pulses of transformer voltage 29 of approximately the duration of half the period of the switching frequency k [iota] * T / 2, kx <1, in which transformer 30 is biased by -BMAX to + BAX and u72 is present at amplitude input U72 at the integrator input, the output voltage of the integrator on line 62 is changing from the negative to the positive maximum value, ie 2 * UMAX.

   This condition applies to push-pull inverters 13 and 26, where kx can advantageously be taken as 1 because the delay time does not change the pulse width. At a minimum operating voltage between time 110 and 112 half the maximum duty cycle of T / 4, in which transformer 30 is magnetized from zero to the maximum value.

   Equation 1 therefore applies: dB / dt = 4 * BMAX / T, and Eq. 1 du62 / dt = 4 * UMAX / T = U72 / (R [iota] N [tau] * CINT)
In the delay time tv111, 112, the induction in transformer 30 increases from the value 152 B55 at time 111 according to equation 1 to the maximum value 116 BMAXan, which is reached at time 112.
B '
'MAX
= B55 + k * B,, MAX with k = 4 * tv / T
G1.2
Analogously, the positive limiting voltage on line 55, so that UX is not exceeded by u62, is calculated according to Equation 2
Ü55 = UMAx * d-) G1.3
Equation 3 in Equation 1 and resolved after R [iota] NT yields: INT = (1-k) * U72 * T / (4 * U55 * C [iota] NT) G1.4
At e.g. U55 = 1.8V, C [iota] NT = InF, U72 = 2V, T = 32 [mu] s and tv = l [mu] s is calculated as RINT to R [iota] NT = 7.8 k [omega].
For double DC link voltage, k2 = 2, the curve 151 is entered in FIG.

   The maximum magnetization 116 is reached at time 155, which lies exactly in the middle between times 110, in which switch 8 turns on, and time 112, in which it switches off again at minimum DC link voltage. Device 40 now has to ensure that the control signal for switch 8 is already withdrawn at time 154, the delay time tv before time 155. The ratios shown correspond to the above realistic numerical example.
Should the inverter now in a wide
Input voltage range UZK, MIN <Uz [kappa] <k2 * Uz [kappa], MiN k2> l, it should be noted that the difference BMAX¯ B55 is the factor k2
B '
'MAX
- B
55.2
= k7 <R> k * B
MAX
G1.5 enlarged.

   Transformer 30 would turn off without further precaution until time 157, because the
Integratorausgangsspannung in device 40, the value 152 reached only at time 156.
The core of transformer 30 would have to be designed to the maximum value 158 BMAX, 2, which is calculated as BMAX, 2 - BMX¯ B55 [iota] 2+ B55. The factor ÜD, by which the core cross-section must be increased,
ÜD = BMAX, 2 / BMAX - 1 G1. 6 is given in Equations 2 and 5 in this case
ÜD = k (k2-l). G1.7 In the case shown, when the supply voltage is doubled, ÜD = 12.5%.

   This oversizing is economically justifiable, whereby push-pull converters can also be used in this field of application.
Cost-effective as a reasonable overdimensioning of transformer 30, according to the method, for example, the voltage U55 after
U55 / 2 = UMA d "k2 * k) Eq. 8 can be reduced in proportion to the increase in the intermediate circuit voltage, which is particularly easy to implement digitally.
For example, starting from magnetization curve 150 with minimum supply voltage of the inverter, the integration speed of the fed-back transformer voltage 72 may be proportional to the increase of the intermediate circuit voltage 35 Uz [kappa] by the factor k2.

   are slightly increased relative to the actual increase in magnetization in the core of transformer 30.
In Figure 8, the course is 159 of
Integrator output voltage U62, KORR entered on line 62 for the case of the supply of the inverter with double DC link voltage, which differs from the actual magnetization curve 151.

   Because the voltage value 152 on line 55 was not intervened, the curve 159 increases slightly steeper than the actual magnetization curve 151, so that the value 152 is also reached at the time point 154.
In the following, for this approach, the current IKORR is calculated which, in addition to the current IINT = U72 / R [iota] N [tau], which corresponds to the amplitude U72 of the fed-back transformer voltage 72, is to be fed to the integrator 73.
The course of the actual magnetization corresponds to the integration of the course of II T, which results from Equation 1 with the setting of k from Equation 2
IINT / CINT = k2 * k * UMA / tvGl. 9 calculated.

   IINT is in the time interval 100, 155 exclusively a function of the variable DC link voltage IINT =
I lN (k2), k2 = UZK, MAX / UZK, MIN -
From the slope of U62, KORR, the required charge current of CI is given by Equation 10.
(IKORR + I INT) / CINT = k2 * k * (1 - k) UMAX / ((1 - k2 * k) * tv) G1. 10
From Equations 9, 10, the nonlinear expression for IKORR / IINT is given by Equation 11,
IKORR / I INT = k * (k1-l) / (l-k2 * k), Eq. l l by the linear expression
I CORR. LIN / I INT = k * (k2-1) / (l-k2f MAx * k), G1. 12 is replaced.

   With k2 from Equation 2 the correction current IKORR, LIN TO IKORR, LIN = k * (Uz [kappa] ¯ UZK, MIN) / (Ü * RINT * dk2, MAX * k)) is calculated with Ü = N [iota] / N2,
G1. 13 which can be considered by analog circuit in the simplest way, where ü is the transmission ratio of the voltage converter 49.
Obviously, the linearized expression from Equation 12 is true for k2 = 1, which must be assumed in the current sizing of transformer 30, and k2 = k2 / MAx, for which the transformer core must be designed.
According to equation 11, IKORRiriit increases
DC link voltage disproportionately, which is why the linear approximation in equation 12, which is inexpensive to implement,

   for intervening values of the DC link voltage, a slightly smaller correction current and results and BMAX is slightly exceeded.
In order to calculate the factor ÜD for overdimensioning, first the value of k2 'is determined where the largest error occurs. <*> < '>
The error function F is defined in Equation 14. .... J.

F <"> (IKORR <¯> IKORR, IN) / IINT G1. 14 I * t
Since IKORR is considerably smaller than II Tist, a small error is to be expected.
The value for k2 'results from the condition 16. The error function F with the expressions used for IKORR and IKORR, LIN from the equations 11, 12 must be derived after k2 and set to zero. dF / dk2 = 0, for k2 = k2 'G1.15
For small values of k, thermals with higher powers of k can be neglected.

   This neglect is allowed if condition 16 is satisfied by the law of k in Equation 2. tvT / 4 G1.16
The delay time may only be a fraction of one quarter of the period of the switching frequency. This condition is usually met. As expected, the largest error occurs in the middle of the operating voltage range: k2 '= (l * k2, MAx) / 2 G1.17
Either the slightly lower utilization of the transformer 30 in the middle operating voltage range is allowed, or it is designed so that it can transmit the full power in this area. The transformer is then designed not to BMX, but to the maximum core inductance BMAX, 2, which then occurs at the operating voltage range limits. With complete compensation, BMAX would occur at the range limits.

   The following applies:
BMAX, 2 / BMAX <=> (I INT + I CORR, LIN) / (I INT + I CORR) G1. 18
 
For ÜD from equation 6, the overdimensioning factor ÜD is finally calculated using equations 9, 11 and 12 as:
ÜD = (1- k2 < '> * K) <2> / ((.-K) * (1-k2, MR [chi] * k)) - 1 G1.19
With the exemplary realistic values, to which FIG. 8 is also based, the value for ÜD is ÜD = 1/168 = 0.6%. From a practical point of view, this method allows the operation of the inverter 13, 26 at variable supply voltage compared to the known prefilter method, wherein the core of transformer 30 can advantageously also be designed for the smallest supply voltage.

   The device 40 required in the process diagram Fig. 5 is shown in Figs. 6, 9 executed.
Fig. 9 shows a simple circuit for correcting the magnetization signal with variable DC link voltage according to equation 13. The circuit shown is the input side to the lines 47, 48 and the output side to line 60, that is connected in parallel to the integration resistor 58 R [iota] NTin Figure 6. Furthermore, it is assumed that the same positive and negative amplitude of the fed-back transformer voltage 72 amounts to 2.5 volts with a minimum DC link voltage.

   This is the zener voltage across the diodes 52 and 53 in FIG. 6, respectively, which define the potentials tapped from the lines 55 and 56 plus the diode forward voltage of the diode 162 and 163, respectively.
With line 47 of the circuit, the feedback transformer input voltage u72 = u29 / ü is supplied, the amplitude of which corresponds to half, in the case of the half-bridge inverter, or the full DC link voltage. This is taken into account in the dimensioning of the transformer 30, so that the described conditions occur.
On line 47, the resistors 160, 167 are connected. Line 161 connects the second terminal of resistor 160 to the negative differential input of buffer amplifier 168, the input of diode 162 and the output of diode 163.

   The output of diode 162 is connected to the output of amplifier 165, which buffers the voltage on line 55. The input of diode 163 is connected to the output of amplifier 166, to which the voltage of line 56 is loaded.
The transmission ratio ü of the voltage converter 49 is selected so that the diodes 162, 163 just do not engage when the inverter is operated at the minimum intermediate circuit voltage. Advantageously, this eliminates another voltage divider.

   If a higher operating voltage, so the positive pulses of the fed-back transformer voltage 72 are clamped by diode 162 to the potential of the line 55 and diode 163 connects during the negative pulses the output of amplifier 166 to line 161, so that the voltage of line 161 of the minimum DC link voltage in positive or negative direction
*
equivalent. The voltage on line 161 is available at the output of the amplifier 168 on.
Resistor 167 is connected to the negative differential input of amplifier 164 and one terminal of resistor 169 whose second terminal is connected to the output of amplifier 164. The positive differential input of the amplifier 164 is connected to line 48.

   The resistors 167, 169 are ideally equal in magnitude and Ri, so that at the output of amplifier 164 on line 170, a voltage is present during the positive pulses of the voltage 72 of the current DC link voltage in the negative direction and during the negative pulses of the voltage 72 of the current DC link voltage in the positive direction corresponds.
The positive differential input of summing amplifier 171 is connected to line 48. The negative differential input is connected to the summing point to which resistors 172, 173 and 174 are connected. The second terminal of resistor 172 is connected to the output of amplifier 168, the second terminal of resistor 173 is connected to the output of amplifier 164 and the second terminal of resistor 174 is connected to the output of summing amplifier 171.

   The output of the summing amplifier is connected to the resistor 175 RKORR whose second terminal is on line 60. The resistors 172, 173 are ideally equal in size, Ri72 = R [iota] 3.
The amplitude UKORR of the output voltage of the summing amplifier 171 is calculated as:
UKORR = (U2K-UZK, MI) * RI74 / (Ü * RI72) G1.20
During the positive pulses of the voltage 72, the positive current IKORR, IN integrator 73 is additionally fed during the negative pulses -IKORR, LIN-
IKORR, IN = + - (Uz [kappa] - UZK, MIN) * Ri74 / (ü * R [iota] 72 * RRORR) G1. 21
Equation 13 calculates the resistance RKORRZU:

  
RKORR = i75 = RiN [tau] * R3 * (l-k2, MAX * k) / (k * R2) G1. 22
With the k = 1/8 and k2 MAX = 2 given previously in the game, RKORRZU RKORR = 7 * RINT * R [iota] 74 / R1 2.
In Fig. 11, logic circuit 79 for the
Full-bridge inverter with phase shift control shown in Fig. 2. FIG. 10 shows the time profiles of the essential quantities on the basis of the diagrams 124 to 131.
Diagram 124 shows the ramp signal 132 with ideal linear rise and infinite slope of the falling edge generated by modulator 43. Furthermore, the controller output signal 95 is entered, the modulator 43 is supplied from the controller output on line 42.

   In the case shown, the controller output voltage is at its upper limit, which is just below the amplitude of the ramp voltage, because in the case shown for higher DC link voltage of
 
For example, the transformer protected according to the invention can not transmit the required power.
Diagram 125 shows the switching states 133, 134 output by modulator 43 on the basis of voltage 95 on lead 45 for the leading bridge branch with the switches 14, 17. Diagram 126 shows the switching states 133, 134 for the trailing bridge branch with switches 20 output on line 46 23. In state 133, switch 17 is closed in the leading branch, switch 14 is open, and line 4 is connected via line 2 to the negative pole of the DC voltage supply.

   In the trailing branch, switch 23 connects line 3 to the negative pole of the DC power supply, and switch 20 is open. State 134 of the leading branch means that the closed switch 14 connects line 4 to line 1, which is connected to the positive pole of the DC voltage supply and switch 17 is open. At the
Trailing branch line 3 is connected by switch 20 to the supply line 1 and switch 23 open (Fig.2). < ">

Modulator 43 generates e.g. the control signal on the leading bridge branch line 45 by specifying the switching timings with the start times of the ramp signal 132. The switching times of the signal on lead 46 for the trailing bridge branch are e.g. determined at equality of the regulator output voltage 95 with the ramp signal 132.

   In the illustrated case, modulator 43 generates in this way two switching-frequency square-wave voltages with the maximum turn-on times of 50%, wherein the signal on line 46 lags the signal on line 45 by almost 180 [deg.], Or half a period of the switching frequency.
At time 135, the leading branch has switched and line 4 is connected to line 1. The trailing branch connects line 3 to supply line 2. The transformer circuit 30 is the DC link voltage in the positive direction and there is a re-magnetization, which would end the control signal on line 46 for the trailing branch after almost half a period of the switching frequency, at time 138 ,

   The nuclear magnetization reaches its critical value, which is fixed on line 55, but already at time 136.
It can be seen that the magnetization of transformer 30 in diagram 127, as well as the transformer primary voltage 29 in diagram 131 from the modulator 43 on lines 45, 46, correspond to a lower phase shift, according to the now permanently engaged device 40 ,
Diagram 128 shows the output voltage of flip-flop 65 on line 75. Flip-flop 65 is set at time 136 in which the magnetization has reached the positive value set on line 55 and remains set to the end of the maximum pulse width at time 139.

   Due to the ORing of the signals on lines 75 and 46, this gives

a

 
Control signal for the trailing branch on line 6 from time 136, the operating state 134 off.
A delay time later, composed mainly of the drive cycle time and the switch delay time of the power switches, at time 137, when the trailing branch switches and voltage 29 becomes zero, the magnetization has grown to its positive maximum value and remains at the leading time until the next time 140 Branch stored.
By switching the leading branch, the negative DC link voltage is applied to transformer 30, as shown in diagram 131, and the remagnetization takes place in the negative direction.

   The critical negative induction value corresponding to the voltage on line 56 is reached at time 141. Comparator 64 responds and resets flip-flop 66 with its output on line 81. Flip-flop 66 is set again only at the end of the maximum duty cycle by the rising edge of the signal on line 45 at time 143. The ANDing of the signals on the lines 46 and 76 causes the operating state 133 is output on line 6 from time 141. At time 144, the leading branch switches, causing the positive intermediate circuit voltage to be applied to transformer 30 again.

   One period of the switching frequency has passed and the sequence described from time 135 is repeated again.
The operating state 134 on line 46 appears to be shifted forward by the operation of the logic circuit 79 on line 6 by the same time periods between the times 136, 138, and 141, 142, whereby the positive and negative pulse of voltage 29 is shortened equally so that the maximum induction in the core of transformer 30 is also not exceeded due to a higher operating voltage and too high a load.

   If a variable DC link voltage is also considered in device 40, e.g. includes the circuit in Fig. 9, so transformer 30 can be designed for the rated power of the device.
FIG. 11 shows by way of example a logic circuit 79 for the full-bridge inverter with phase-shift control. As can be seen from the diagrams 15, 126, a shortening of the drive phases takes place when the trailing branch switches over prematurely. Circuit 79, for example, only changes the control signal for the trailing bridge branch output by modulator 43 on line 46 with the switches 20, 23. Line 45 is connected to line 5.

   The control signal for the leading branch is not intervened.
The positive pulse of voltage 29 is shortened by the control signal on line 6 against the signal on line 46 prematurely switched from the operating state 133 to the operating state 134. The OR gate 146 is the input side to the lines 46 and 75, the output side to line 145th
- 25 connected. Line 75 is connected to the output of negatively edge-triggered RS flip-flop 65, which is consistently reset when the leading branch control signal on line 45 transitions from operating state 134 to operating state 133. In FIG. 10, this takes place at the time 139, whereby, after the delay time tvzum at the time 140, the intermediate circuit voltage is applied to the transformer 30 in the negative direction.

   Time 139 marks the end of the theoretically achievable length of the positive pulse of primary voltage 29. Flip-flop 65 is set by the output of comparator 63 on line 80. Comparator 63 can only respond within a positive voltage pulse 29, while line 46 has the operating state 133 (LOW). Only when comparator 63 has responded, such as at time 136 and line 75 has the operating state 134, does the gate enter <*> <*> 146 on line 145 against the signal on line 46 the operating state 134 (HIGH) off. Line 145 and line 76 are connected to the input of AND gate 147 whose output is routed to control line 6.

   During a positive voltage pulse 29, line 46 has the a> operating state 133, line 76 is in operating state 134, so that the premature change of the operating state from 133 to 134 on line 75 compared to line 46 to the lines 145 and 6 is turned on. The positive pulse is removed from time 137 until start time 140 of the negative voltage pulse from transformer 30, so that it does not saturate in the positive direction.
Line 76 is connected to the output of the negative edge-triggered RS flip-flop 66. Line 149 connects the output of inverter 148 to the SET input of flip-flop 66. The input of inverter 148 is connected to line 45.

   Flip-flop 66 is constantly set by the signal on line 45 at about time 143 when it transitions from operating state 133 to state 134 and a positive pulse of primary voltage 29 is started. The negative pulse of voltage 29 will shorten a delay time after time 141 in which comparator 64 responds and flip-flop 66 is reset from the signal on line 81 until time 144, a delay time after time 143. This in turn can only happen during a negative voltage pulse 29, while the lines 46, 145 have the operating state 134. The signal on line 6, together with the signal on line 76, then prematurely changes from state 134 to state 133 at time 141 opposite the signal on lines 46 and 145.

   The negative DC link voltage, the delay time is removed after time 141 until the start time 144 of the positive pulse of transformer 30 so that it does not saturate in the negative direction.

a>

Now, in this method when operating the inverter to a substantially constant intermediate circuit voltage and constant delay time, in particular in the full-bridge inverter with phase shift control, can be dispensed with the feedback. In FIG. 12, the voltage converter 49 is omitted from FIG. 4 because [iota] induction limiting device 50 predicts the course of the magnetizing current directly from the signals 5 and 6.

   This method requires a sufficient constancy of the delay time tv, so that the operating states 96, 97 of the half-bridge inverter and 133, 134 of the full-bridge inverter with
Phase shift control, or the duration of the positive and negative pulse of the primary voltage 29 within a period of the switching frequency sufficiently accurate with the duration of the operating states 96, 97, and 133, 134 on the control lines 5, 6 matches.

a

Fig. 13 shows the circuit diagram of a according to this principle
working device 50 for the half-bridge inverter in Fig.1.

   Compared with device 40 in FIG. 5, the transformer voltage 72 fed back between the input lines 47, 48 of the integrator 73 is replaced by a voltage 199 reproduced by means of the signals on the control lines 5, 6 for the power switches 8, 11.
Line 47 connects the integrator input to the output of switch 178 and the input of switch 180. Input of switch 178 is connected to line 55, at which the positive limit voltage is present. The output of switch 180 is connected to line 56 at which the negative limit voltage is present. The voltages between line 55 and line 48, and between line 48 and line 56 are the same size, see Fig.6.
The control signal on line 5 for power switch 8 is supplied to the input of the control means 177 for switch 178.

   The input of the control device 179 for switch 180 is connected to control line 6 for power switch 11.
When the operating state 97 for switch 8 is output on line 5, switch 180 is actuated and the voltage on line 56 is applied to the input of the integrator, line 47, whereupon, according to the closed switch 8, the magnetization of transformer 30 increases closed switch 180 and the magnetization signal on line 62nd

   If line 6 is in operating state 97, power switch 11 and switch 178 are engaged, whereupon the magnetization of transformer 30 and the voltage on line 62 increase in the negative direction.
In circuit 197 of Figure 5, which is equally connected on the input side to the lines 45, 46, 80,81 and the output side, the control lines 5, 6 supplies, logic circuit 78 in Fig.6 to use.
In contrast to the known prefilter method, any reduction of the pulse width of voltage 29 is permissible,
a
.J
wherein the magnetization in transformer 30 at the reduced pulse width has a DC component which decays in time. Now, the theoretical case can occur that after many switching periods, the controller 41 suddenly again requires a large pulse width.

   If, for example, the transformer 30 was magnetized in the negative direction, in contrast to the known prefilter method it is also possible to increase the following positive pulse to almost the full pulse width. However, if the magnetization at this time has already subsided to a large extent, then, as in the known methods, for the time being only the increase to half the maximum pulse width is permissible, otherwise the transformer 30 would have to be designed for twice the power for this theoretical case.

   Therefore, demagnetizing effects, such as the primary-side or secondary-side linear demagnetization, are proposed against the valve-line voltages in the freewheeling intervals and / or the exponential decay of the [iota] with a large time constant.
Equal magnetization according to the sum of the underlying in each circuit resistances to take into account.
Fig. 14 shows an example of such an extended 1
Integrator circuit 73 in Figure 5 for the full bridge converter with phase shift control in Fig.2. The circuit is <> with reference to diagrams 200 to 210 in FIG. 15.

   Induction limiting device 50 in Figure 5 therefore consists of limiting device 197, in which now the logic circuit 79 is to be used in Figure 11 and integrator 73 of FIG.
Circuit 197, the magnetization signal on line 62, as well as on line 45, the control signal for the leading branch, the switches 14, 17, and on line 46, the control signal for the trailing branch, switches 20 and 23 is supplied. The control lines 5, 6 connected to the outputs of circuit 197 are fed back to the input of the integrator circuit 73 in FIG. 14 or control integrator 73 in the drive phases by means of the electronic switches 178, 180.
Fig. 15 shows the essential waveforms within a period of the switching frequency of the inverter in Fig. 2 for a steady state operation.

   Diagram 200 shows the leading branch control signal on lines 5, 45 connecting loop circuit 79. Diagram 201 shows the control signal for the trailing branch whose phase shift corresponds to the value at the controller output. The transformer magnetization is not critical and circuit 197 is not engaged, the signal on line 46 is turned on on line 6.
One input of the XOR gate 181 is connected to line 5, the other to line 6. Line 182 connects one input of AND gate 183 and one input of AND gate 184 to the output of XOR gate 181. The other input of gate 183 is on line 5, the other input of gate 184 is connected to line 6.

   Line 185 connects the output of

[Iota]
 
Gate 183 with the input of the control circuit 179 for switch 180, which is connected to the output side to line 56 and the input side to line 47. Line 186 connects the output of gate 184 to the input of the control circuit 177 for switch 178, which is connected on the output side to line 47 and on the input side to line 55. For the transistors 178, 180 are due to the accuracy and because then the control circuits 177, 178 are very simple, paired p and n transistors used.
Diagram 202 shows the voltage 199 applied to lines 5, 6 to the integrator input, on line 47, in the negative count direction.

   It can be seen that the gates 181, 183 and 184 serve to not simultaneously turn on both switches 178, 180 from time 219 to 220 and thus to apply the potential of line 48 to the integrator input, line 47. Diagram 203 shows the output of the XOR gate on line 182. Diagram 204; shows the output of gate 183 on line 185, which drives switch 180 and generates the negative pulse of voltage 199, while on power transformer 30 - shifted only by a delay time, the positive pulse of voltage l 29. According to the inverting
Operational amplifier circuit 58, 59, 61, 48 rises <>
Magnetizing signal on line 62, corresponding to the actual magnetization of transformer 30, on.

   Diagram 205 shows the control pulse on line 186 for switch 178 which is closed when inverter 26 applies negative DC link voltage to transformer 30 and the transformer magnetization and accordingly the output voltage of integrator 73 between lines 62, 48 decreases.
Furthermore, it can be seen that voltage 199 has no delay time with respect to the control signals and its amplitude U55 minus the switch circuit voltage UF of the switch is 178 and 180, respectively.

   The integrating resistor 58 R [tau] connected to the lines 47, 60 is therefore calculated from Eq. 1 with ki = 1, UMAX = U55 and U72 = U55-UF
RINT = T U55 - UF) / (4 * U55 * CINT) Eq. 24
With the exemplary values T = 3-2 [mu] s, U55 = 1.8V, C [iota] NT = InF and UF = 0.3V, RTNZU RTNT = 6.7k [Omega] is calculated.
The magnetization of transformer 30 is determined during the drive phases by driving the switches 178, 180. Two further switches 187, 188 are engaged during the freewheeling intervals.
The embodiment of the integrator 73 in FIG. 14 has a further input which is connected to line 193, which is connected either by means of switch 187 <'> Line 55 or by means of switch 188 is connected to line 56, or remains open during the drive phases.

   With resistor 194 RNT, which is connected on the one hand to line 193 and on the other hand to line 60, the linear demagnetization of
 
Transformer 30 is considered in the freewheeling phases against the valve flux voltages UVF. UVF sets each, whether via switch 14 and diode 21 or switch 20 and diode 15 in the upper freewheel via supply line 1 or in the freewheeling phases via supply line 2, in which either switch 17 and diode 24 or switch 23 and diode 18 stro are end, from the sum of a diode and a switch voltage together.

   The direction in which integrator 73 has to integrate its input on line 193 depends solely on the instantaneous magnetization of transformer 30 at the end of the drive phase, or at the beginning of the freewheeling phase, because it counteracts the cause.
Line 62 is therefore further routed to the negative differential input of comparator 213 whose positive differential input is connected to line 48. The output of comparator 213 routed on line 216 is HIGH when transformer 30 is negatively magnetized, or the integrator output voltage of line 62 on line 48 is negative and LOW at positive magnetization. Furthermore, an input of the AND gate 192 and the input of the inverter 214 is connected to line 216. Line 215 connects the output of inverter 214 to an input of AND gate 191.

   The signal on line 215 is shown in diagram 207. It indicates the magnetization state of transformer 30. The other inputs of the AND gates 191, 192 are connected to line 217, which is supplied by the output of the inverter 218. At the input of inverter 218, the signal is on line 182 in diagram 203.
Diagram 206 shows the signal on line 217 which is high during the freewheeling phases and LOW during the freewheeling phases. If the transformer magnetization is now negative, the AND gate 192 switches the freewheeling signal of line 217 to its output on line 195, as shown in diagram 209. Switch 188 is turned on by controller 190 and the negative voltage of line 56 is applied to the integrator input on line 193.

   With negative magnetization of transformer 30, the integration takes place in the positive direction.
When transformer 30 is positively magnetized, the flywheel signal from line 217 is fed from AND gate 191 to line 196, whereupon controller 189 closes switch 187 and the positive voltage from line 55 is applied to the input on line 193, whereupon this input turns on Integration takes place in a negative direction. Diagram 208 shows the control signal on line 196 for integration in the negative direction.
When the magnetization signal crosses the zero potential within a freewheeling interval coming from positive or negative direction, comparator 213 reverses the direction of integration, whereby the magnetization signal is kept zero over the following drive phase until the beginning of the next freewheeling phase or

   Integrator 73 stopped
>

 
is, as it corresponds to the actual conditions in transformer 30.
Diagram 210 shows the magnetization of the transformer 30 or the magnetization largely corresponding course of the magnetization signal, which simulates the magnetization in the drive phases and the demagnetization in the freewheeling phases.
Dash-dotted another course 212 of the magnetization is registered, which moves only in the negative range. Comparator 213 does not switch, as shown in broken lines in Diagram 7. The freewheel signal in diagram 206 continues to be routed on line 195, as shown by the dot-dash line in diagram 209. Therefore, in the freewheeling interval from time 119 to 120, curve 212 has a positive slope, while curve 211 has a negative slope in this period.

   From trace 212, it can be seen that the negative DC magnetization steadily decreases due to the low demagnetization in the freewheeling intervals.
  <EMI ID = 31.1>

  <EMI ID = 31.2>

The magnetization speed is proportional to the applied voltage. If it is a factor K in the propellant phase, it is the factor K * UVF / UZK in the freewheeling phase. Similarly, the speed of integration has to behave the currents
If the maximum pulse width of 100% from one pulse to the next is permanently reduced to 0%, the transformer magnetization degrades as a result of the demagnetization against the valve flux voltages in time TE = T * UZK / (4 * UVF).

   In the numerical example, TE20 is periods of the switching frequency of the inverter.
LH = lmH, Ri = lOOm [omega], CINT = InF, gives resistance 198 RD to RD = 10 M [omega].
The values for REN [tau] and RD from the numerical example show that here the linear demagnetization against the valve flux voltages in the freewheeling phases outweighs the demagnetization due to the weak damping by an order of magnitude.
REFERENCE NUMBERS:
1 supply line ....
2 supply line * ....
3 line. **.
4 line * ..... <>
5 line:

   : *:
6 line <*>
7 drive circuit.
8 switches
9 diode:.
10 drive circuit -
11 switches
12 diode
13 inverters
14 switches
15 diode
16 drive circuit
17 switches
18 diode
19 drive circuit
20 switches
21 diode
22 drive circuit
23 switches
24 diode
25 drive circuit
26 inverters
27 capacitor
28 capacitor
29 transformer primary voltage
30 transformer
31 supplying network
32 input rectifiers
33 output rectifier
34 load
35 Supply voltage, DC voltage, DC link voltage
36 line
37 line
38 line
39 line
40 device
41 controllers
42 line
  <EMI ID = 33.1>
 
118 time
119 amplitude
120 time
121 value
122

   123 times 124-131 diagrams
132 ramp signal
133 operating state
134 Operating state 135-144 times 145 Line
146 OR gate
147 AND gate
148 inverters
149 direction
150 magnetization curve
151 magnetization course
152 value
153 value
154157 times
158 value
159 magnetization course
160 resistance
161 line
162, 163 diodes
164166 operational amplifier
167 resistance
168 operational amplifiers
169 resistance
170 line
171 operational amplifier
172175 resistors
176 line
177 drive circuit
178 switches
179 drive circuit
180 switches
181 XOR gates
182 line
183, 184 AND gate
185, 186 lines
187, 188 switches
189, 190 drive circuits
191, 192 AND gate
193 management
194 resistance
195, 196 lines
197 Induction limiting circuit
198 resistance
199 tension
200210 diagrams
211, 212 Magnetization gradients
219

   220 times
  <EMI ID = 34.1>
221 resistance

a
222 zener diode


    

Claims (21)

claims 1. A method for controlling alternately switched to a DC voltage transformers, in particular of pulse width modulated half and full bridge converters or phase shift controlled full bridge converters or inverters, wherein either a primary coil of the transformer or the DC supply voltage is alternately reversed and a period of time over which the primary coil positive or negatively connected to the DC voltage circuit, depends on a required amount of output of a connected to a secondary winding of the transformer, preferably via a rectifier consumer, characterized in that a device 40 or 50 receives a signal or self-generated, that of the primary voltage at the transformer corresponds, then generates a magnetization signal,  which corresponds to the magnetization of the transformer, continuously compares the magnetization signal with a positive and a negative critical value set in device 40 or 50, and device 40 or 50 a period of a positive or negative pulse generated at the required change in output magnitude at the primary winding of the transformer shortened when the magnetization signal has reached the positive or negative critical value. (Figs 4, 5) 2. The method according to claim 1, characterized in that the magnetization signal generates an integrator which integrates the signal corresponding to the transformer primary voltage. 3. The method according to claim 1 or 2, characterized in that the transformer primary voltage is fed back to the device 40. 4. The method according to one or more of claims 1 to 3, characterized in that an increase in the supplying DC voltage leads to a magnitude reduction in size of the positive and the negative critical value in device 40. (Fig.8) 5. The method according to one or more of claims 1 to 4, characterized in that an increase in the supplying DC voltage in device 40 causes an increase in the integration speed. (Figs. 8, 9)  6 of the logic circuit 78 or 79 determines the periods 99, 100 of positive and negative voltage pulses on the transformer. (Figs 6, 7) 6. The method according to claim 1 or 2, characterized in that device 50 controls the integrator with its output signals. (Fig. 13) 7. The method according to claim 6, characterized in that the magnetization signal, when the pulse width is withdrawn at the transformer decreases in terms of amount. 8. The method according to claim 7, characterized in that the magnetization signal decreases linearly in the freewheeling intervals. (Figs. 14, 15) 9. The method according to claim 7, characterized in that the magnetization signal is weakly attenuated during demagnetization, or during the entire period of the switching frequency of the inverter. (Fig. 14) 10. Device 40 according to one or more of claims 1 to 3, characterized in that at the input of an integrator 73 from the output of a Voltage detector, e.g. a magnetic voltage converter 49, which is connected in parallel on the input side of the primary winding of transformer 30, is supplied with a signal 72 corresponding to the transformer primary voltage 29, the output of the integrator 73 is fed to the input of a comparator 63, at its second input a positive critical Value 55, the output of integrator 73 is connected to the input of another comparator 64, to whose second input a negative critical value 56 is fixed, the outputs of the comparators 63, 64 are respectively connected to an input of a logic circuit 78 or 79 in that the logic circuit 78 or 79 on further inputs receives the durations of the pulses 45, 46 generated in response to a required change in the output quantity, and device 40 with its outputs 5, 11. The device 40 according to one or more of claims 1 to 5 and claim 10, characterized in that an input resistor 58 of integrator 73 is selected so that the magnetizing signal occurring at the integrator output 62 upon application of the maximum operating voltage to the primary winding of transformer 30 within half the period of the switching frequency of the inverter from the negative 56 to the positive critical value 55 increases. 12. Device 40 according to claim 11, characterized in that integrator 73 is added a further input resistor 175 to an input 176 to which a signal from an amplifier 171 is applied, which also follows the course of a fed-back transformer voltage 72 and its amplitude of the height the DC supply voltage minus its lower limit, the amount of minimum operating voltage is proportional. (Fig. 9) Device 40 according to claim 12, characterized in that the magnitudes of the critical values 55, 56 are equal to the amplitude of voltage 72 at minimum operating voltage minus the forward voltage of a clamping diode 162 or 163. Device 40 according to claim 12 or 13, characterized in that the diodes 162, 163 limit the amplitude of the signal following voltage 72 at the input 161 of a buffer amplifier 168 to that amount corresponding to the minimum operating voltage, an operational amplifier 164 voltage 72 inverts and operational amplifier 171 inverts and adds the output signals of the operational amplifiers 164, 168, so that the Amplitude of the signal at its output 176 of the supplying DC voltage minus its lower limit is proportional. 15. Device 40 according to one or more of claims 12 to 14, characterized in that resistor 175 is dimensioned according to equation 22. 16. Device 50 according to claim 1 or 2, characterized in that the output at the outputs 5, 6 of the logic circuit 78 or 79 period for the positive and the negative pulse to transformer 30 and integrator 73 controls. (Fig. 13) 17. Device 50 according to claim 16, characterized in that the input resistor 58 of integrator 73 is selected such that the occurring at the integrator output 62 Magnetizing signal when applying a constant voltage, advantageously the positive critical voltage 55 to resistor 58 within half a period of the switching frequency of the inverter of the negative 56 to the positive critical value 55 increases. 18. The device 50 according to one or more of claims 8, 16 or 17, characterized in that the integrator 73 is added to another input 193 with input resistor 194 whose duration of engagement of the outputs 5, 6 of the logic circuit 78 or 79 is determined and its direction of engagement is controlled by the output of a comparator 213 whose output 216 indicates whether the magnetization signal is positive or negative. (Figs. 14, 15) 19. Device 50 according to claim 18, characterized in that input resistance 194 is dimensioned according to equation 27. 20. The device 50 according to claim 18 or 19, characterized in that the logic circuit 79 is used and the engagement time of the Inte [sigma] ratoreinganges 193 is determined by an XORVerknüpfung the signals on the control lines 5, 6. 21. Device 50 according to claim 9 and one or more of claims 16 to 20, characterized in that an integration capacitor 59, a damping resistor 198 is connected in parallel.