AT505507B1 - METHOD AND DEVICES FOR RESTRICTING INDUCTION IN THE CORE OF FORMALLY TRANSFORMERS SWITCHED TO AN EQUAL VOLTAGE - Google Patents

Abstract

In the devices 40 (FIG. 6) and 50 (FIG. 13) according to the invention, an observer or integrator 73 is installed which tracks the magnetization of the power transformer 30 connected to a push-pull inverter 13 or 26 on the output side, which constantly monitors in device 40 or 50 is such that the magnetization of the power transformer within a 40 and 50 internally fixed positive and negative limit moves in the linear range and leaves this also in no operating condition. For this purpose, the inverter output voltage or primary voltage 29 is fed back to the input of the observer either at device 40 via a measuring device 49 (FIGS. 4, 6) or a voltage generated within the device 50 (FIGS. 12, 13) from the control signals 5 and 6 applied, which anticipates the course of the primary voltage 29. In contrast to device 50 in the observation signal, device 40 also takes into account the level of intermediate circuit voltage 35. As a rule, device 40 or 50 switches the control signals 45, 46 present at the beginning, which are predetermined by the application process via controller 41 and pulse pattern generator 43, to control lines 5 and 6 of the inverter by. However, when the magnetization signal at the output of the integrator reaches the positive or negative limit during a positive or negative pulse of the primary voltage 29, the corresponding control signal on line 5 or 6, which just determines the duration of the positive or negative voltage pulse of the primary voltage 29, of the device 40 or 50 shortened immediately compared to the corresponding signal on line 45 or 46. (Figs 6,13)

Description

Austrian Patent Office AT505 507B1 2010-03-15

Description: The invention relates to a method for controlling alternately switched to a DC voltage transformers, as described in the preamble of claim 1.

The economic importance of push-pull converters or inverters that switch a DC voltage alternately in the positive and negative directions to a transformer, consists in the main thing that the power transformer, which significantly affects the cost price, transmit twice as much power at the same core cross-section can because the core of the transformer is magnetized in both directions, rather than just in one direction. With the same switching frequency and the same component cost, but much smaller transformer effort, the full bridge on the same ripple of the output current, as the two offset by 180 ° but otherwise independent of each other working forward converter in EP 0483897 A1 (TELEFONAKTIEBOLAGET LM ERICSSON) from 1992. It can think of the two forward converters to the full bridge in parallel and switched to only one of the two transformers, one of the positive and the 180 ° offset forward converter generates the negative pulse of the primary voltage (conventional control of the full bridge).

The exploitation of this cost advantage was initially, however, the not yet solved saturation problem of the power transformer with respect to, which represents a very weakly damped integrating path due to its large main inductance and its low internal resistance, taking into account the switch and diode, or valve flux in the linear region , Now, if the positive pulses applied to the transformer by the push-pull structure are only slightly larger than the negative ones, or vice versa, first due to different driver sweep and switch response times, then this fault will integrate until the transformer suddenly saturates and becomes a short circuit, which leads directly to the shutdown of the device or to its destruction. For applications in which the pulse width changes from the positive to the negative pulse of the primary voltage very slowly, some saturation causes could be partially addressed in special applications, e.g. by the patents of 1979, US 4150424 (NUECHTERLE1N); 1985, US 4553198 A (CHAN et al.) and 1987, EP 0237861A2 (KABUSHIKI KAI SH A TOSHIBA). Oer use of this pulse pattern correction circuit performance of the device calculated.

The economic importance of push-pull converters has only begun to increase in 1990, due to the availability of modern, robust, nearly powerless controllable power semiconductors, such as FET or IGBT, with sufficiently constant and largely load-independent Schaltverzögerungs- and driver turnaround times and driver circuits, with a sufficient fast short-circuit shutdown are equipped. Nevertheless, the scope remained limited to applications with low dynamic requirements until 1994, because rapid regulation arbitrarily generates different positive and negative pulse durations. Saturation of the power transformer due to fast regulation would have to be prevented by saturation detection. The detection of incipient saturation places high demands on the accuracy and speed of the measurement and on the response time even of modern drivers and circuit breakers.

In order to come closer to the theoretically achievable dynamics associated with the switching frequency and for safety reasons, it is still manages today, the power transformer to switch a pulse-resistant capacitor of small capacity in series. The full bridge converter would add a power component. With half-bridge inverters, the support capacitors can be selected to be correspondingly small, so that it is no longer possible to assume a fixed center point voltage. If an application process now requires roughly unequal positive and negative pulse widths due to the fast control, the DC component of the transformer primary voltage is compensated faster, but the voltage at the power transformer is reduced by the capacitive voltage drop, which is why the less power can be transmitted, the more dynamically the inverter is designed. At the same time, the power transformer must be provided with an air gap and over-dimensioned to withstand the transient, lasting several periods of the switching frequency Gleichmagnettsierung until the voltage at the coupling capacitor compensates for the DC component of the primary voltage. Also, the almost undamped resonant circuit, consisting of coupling capacitor and Transformatorenhauptinduktivität, problematic.

Therefore, the push-pull structures remained until 1994 limited to slow-to-control application, such as. in the provision US 4477867 A from 1984, the symmetry of the transformer in the push-pull circuit according to claim 1 is ensured by the fact that the controller ensures that both switches turn off the same peak current. "Means for comparing the rate of increase of the current in said primary winding"; needed.

The invention in the provision US 5550498 from 1996 is characterized by the measurement of the transformer primary current and further characterized in that in the regulator described, the measured primary current is integrated and a signal generated by the power transformer proportional signal is generated, which with the "set voltage " and others by comparing to a shaft action of " Charge mode pulse-width-modulation Circuit " leads. The invention requires a current detector on the primary side.

Both claims do not solve the problem described here of making push-pull converters suitable for applications hitherto, e.g. EP 0483897 A1 (TELEFONAKTIEBOLAGET LM ERICSSON) from 1992 were reserved. The further remarks do not relate to the subject matter of the invention: The provision US 2004/0264216 A1 relates to flyback converters, in particular for singlestage single-switch power-foctor-corrected AC / DC converters " and determines when the energy stored in the transformer has discharged into the output circuit or "a level substantially equal to zero". has reached (claim 1). The invention requires a measuring winding and is not applicable to push-pull converters.

The provision US 2005/0285587 A1 does not relate to the subject of the application, but an apparatus and a method for determining the output current from the primary side of a switching power supply (title). Another controller is described. There will be a " peak detector " and a zero-current detector " needed.

The provision US 7054171 B1 from 2006 does not affect push-pull converters, but the regulation of a single switch. The invention is also based on a measuring device which can detect the ripple current at a previously calculated time after switching on the switch.

The full bridge with phase shift control is so far a special push-pull converter, because the magnetization of the transformer takes place exclusively at the same time with the power transmission and its magnetization in the intervening pauses -the so-called freewheeling intervals - remains almost undiminished. Practical experience with the full bridge with phase shift control and already available modern drivers and circuit breakers has shown that it is sufficient to generate sufficiently accurate control pulses that theoretically - presumptive assumption - does not exceed the maximum allowable magnetization of the power transformer. This effect is achieved by filtering out from the setpoint voltage or regulator output voltage those frequency components which would cause a steady increase in the magnetization. The filter is arranged between controller output and pulse width modulator input, or integrated into the control pulse generator.

In the published patent application of the German Patent Office DE 196 34 713 A1 from 1995 methods are described in which exactly half the pulse width change is passed, so theoretically a maximum magnetization is not exceeded, depending on the amount of arbitrary setpoint changes a direct magnetization is allowed. The filter, which divides each pulse width change into two consecutive pulses, can only be digitally realized. The methods have proven to be practical and led to a significant increase in the dynamic properties of the full bridge, the core of the power transformer can already be advantageously designed without further oversizing and without air gap to the largest operating voltage. The difference in the duration of positive and negative pulses of the primary voltage can already be up to 50% of the maximum pulse duration. In any case, the full bridge with phase shift control could already be upgraded to high dynamic requirements (welding process, plasma hardening) with the digital filter that does not require feedback. The digital filter has also proven itself in the industrial solar converter.

For the full bridge with phase shift control, a device will now also be described without feedback, which ensures that the transformer is operated in the linear range, with mostly any pulse width changes may occur up to 100% of the maximum pulse duration of one to the next pulse of the primary voltage ,

In conventional PWM control of the full bridge, as well as, for example, in the half-bridge balance transformer, a load-dependent demagnetization takes place after the end of a power transmitting time period. There are load-dependent intervals in the primary voltage which are not matched in the control signals. If the inverter is subject to high dynamic requirements, a feedback action may be necessary. The procedure according to the invention with feedback of the transformer voltage is intended to ensure that the transformer is operated in the linear range, which practically is not yet confirmed or given only in a limited manner without feedback. The procedure according to the invention with feedback of the transformer primary voltage has the goal of actually designing the transformer core up to a safety margin to the rated power of the device, ie to the smallest supply voltage or intermediate circuit voltage, also in the half-bridge balance converter and also in conventional closed-loop control of the full bridge.

In both cases, the devices of the invention are connected in the control lines to the driver circuits and only intervene when the power transformer threatens to leave its linear range, according to the invention even before saturation phenomena occur. The present invention should have the dynamics attainable with the full bridge largely aligned with those that can be achieved with the Leistunsteil in EP 0483897 A1 (TELEFONAK-TIEBOLAGET LM ERICSSON).

The present invention has for its object to operate the transformer in the push-pull converter in all operating conditions in the linear range, with cost-effective electronic means, which occasionally cause a pulse shortening the power transformer, regardless of the controller used, or without constant intervention.

In any case, the procedure of the invention with feedback of the transformer voltage also ensures the protection of the transformer at a higher and fluctuating supply voltage, which is naturally not given in the prefilter. For example, in applications such as in the rail network, where a widely varying supply voltage has to be expected, the prefilter method is unsuitable because the transformer is current for the minimum operating voltage, but the core of the transformer is for the maximum operating voltage and the transformer is much greater power would have to be designed, whereas in accordance with the invention the transformer core advantageously also be designed only for the minimum operating voltage and the transformer can be designed for the rated power of the device.

The present invention has for its object to extend the scope of push-pull structures and to make fully usable without sacrificing the reliability of their dynamic resources.

The object of the invention is achieved by the method according to claims 1 to 9 and by the devices according to claims 10 to 14.

In the process according to claim 1, the detection of the non-linear Austrian Patent Office AT505 507B1 2010-03-15 is advantageously unnecessary

Transformator saturation and compared to the known methods is advantageously intervened only in the event of imminent saturation of the transformer not on the controller output but on the output of the pulse width modulator. As a result, the theoretically achievable dynamics of the inverter is again significantly increased. In addition, the procedure of claim 2 is possible because the transformer is operated in the linear range.

In the procedure according to claim 2, the magnetization of the transformer is determined inexpensively by integration of a signal whose course corresponds to that of the transformer primary voltage.

In the procedure according to claim 3, a magnetic voltage converter can be used cost-effectively, which is also operated in the linear range. Furthermore, fluctuating switching delay times are taken into account, which is why it is particularly advantageous not only to use cost-effective pulse width modulators, but also cost-effective driver circuits. Furthermore, any demagnetizing intervals, as well as parasitic effects, such as the symmetrizing effect parasitic switch capacitances and the reduction of the transformer voltage to the forward voltages of the current-carrying valves and the voltage drops across the parasitic resistors and thus also the decreasing tendency of any existing DC magnetization with reduced pulse width fed back, which is why the method can be advantageously applied to all push-pull structures. In any case, the inverter can already be economically operated on variable supply voltage, because the transformer must be dimensioned only for a corresponding to the fluctuation of the supply voltage above the rated power of the device lying power, for example, to 120% of the rated power for supply voltage fluctuations of + -10%.

By the procedure of claim 4 or 5 is advantageously achieved that the transformer core can be designed for the lower limit of the intermediate circuit voltage. The procedure of claim 4 is particularly suitable for digital implementation, while the procedure of claim 5 in a similar manner is particularly simple.

The procedure of claim 6 is useful, with only slightly fluctuating supply voltage of the inverter, e.g. + -10% and especially for the phase-shift-controlled full-bridge inverter. Advantageously, no feedback and thus no voltage converter is needed. Inexpensive, the transformer magnetization is obtained by integration of a signal derived directly from the control signals. It is also advantageous to use a cost-effective pulse width modulator.

In the approach according to claim 7, the decay of the DC magnetization is cost-effectively taken into account for the unlikely event that longer quasi-stationary states are terminated or interrupted by rapid setpoint changes.

The procedure of claim 8 is advantageous if it is essentially a linear demagnetization of the transformer against the sum of the lying in the freewheeling valve voltages. This can also be realized inexpensively by means of a digital counter.

The procedure of claim 9 is advantageous if an exponential decay in the freewheeling phases or an exponentially weakening increase in magnetization is determined by the lying in the respective circuit internal resistances for the demagnetization of the transformer. When executed in conventional analog technology, the possibly determining attenuation by the parasitic resistors can be easily and inexpensively by parallel connection of a correspondingly high-impedance resistor to the integration capacitor taken into account. This procedure is already feasible in digital technology at low cost.

In the procedure according to one or more of claims 7 to 9, the power transformer can be advantageously designed for the maximum operating voltage.

Claim 10 describes a device 40 which can be used for all push-pull converters and variable supply voltage. Claim 11 describes a device 40 according to claim 10, in which the transformer is utilized as well as possible.

The procedure of claim 12 advantageously reduces the over-dimensioning of the transformer beyond the required rated power of the device, especially in applications for a wide supply voltage range.

Advantageously, the procedure according to claim 13 eliminates the need to define two further values for limiting the amplitude of the fed-back transformer voltage.

The procedure of claim 14 represents a cost-effective implementation of claim 12.

By the procedure of claim 15, the required over-dimensioning of the transformer is avoided in particular due to a fluctuating supply voltage.

Claim 16 describes a principle for all push-pull converters in application areas, where an approximately invariable supply voltage is present, suitable device 50, which manages inexpensively without the detection of the transformer primary voltage.

The procedure of claim 17 makes it possible to interpret the core of the transformer not far above those magnetic flux, as that which can occur in steady state operation at the maximum supply voltage.

The procedure according to claims 17, 18 and 19 enables a further reduction of the core cross-section of the transformer, or finally its design for operation at the maximum supply voltage, even in the unlikely event that the application process requires rapid changes of the output, which are interrupted by longer quasi-stationary operating states.

For a better understanding of the invention, this will be described in more detail below with reference to the half-bridge and full-bridge converter.

[0048] [0048] [0048] [0048] [0049]

Show it:

Fig. 1: the schematic diagram of the half-bridge inverter;

Fig. 2: the schematic diagram of the full-bridge inverter with phase shift control;

Fig. 3: Process diagram of a power electronic DC-DC converter according to DE 196 34 713 A 1;

Fig. 4: one of an inverter, which is controlled via a primary side feedback correction circuit, mutually connected to a DC voltage transformer with secondary rectifier and connected to this rectifier loads or the process diagram for claim 1;

FIG. 5: block diagram of the induction limiting device; FIG.

FIG. 6: Circuit diagram for integrator and induction limiting device for the half-bridge counterclockwise converter; FIG.

FIG. 7: time profiles of control signals, resulting transformer voltage and transformer magnetization for the half-bridge inverter in FIG. 1 with induction limitation according to FIG. 6 according to the invention; FIG.

8: magnetization curves at maximum pulse width for different supply voltages;

FIG. 9 shows a circuit expansion for the integrator circuit in FIG. 6 to take account of a variable supply voltage; FIG. 5: 39: Austrian Patent Office AT505 507 B1 2010-03-15 [0050] Fig. 10: Time courses of control signals, resulting transformer voltage and

Transformer magnetization for the full-bridge inverter with phase shift control in Figure 2 with inventive induction limit of Figure 6 with the logic circuit of FIG. 11. Fig. 11: Circuit diagram for an exemplary logic circuit for the full bridge Wechselrich ter with phase shift control in Fig. 2; FIG. 12 shows the process diagram for a non-feedback procedure; FIG. Fig. 13: Circuit example of integrator and a non-feedback induction limiting device for the half-bridge converter in Fig. 1; FIG. 14 shows an example of an extended integrator circuit for the full-bridge inverter. FIG

Phase shift control taking into account the transformer demagnetization tendency; FIG. 15 shows time profiles of the essential variables during a period of the switching frequency of the inverter in FIG. 2 for explaining the circuit in FIG. 14.

Fig. 1 shows the inverter 13, the supply lines 1 and 2 is connected to the output of a voltage intermediate circuit, such as the capacitor at the output of a mains rectifier. To the lines 1 and 2 two connected by line 3 in series capacitors or voltage sources 27 and 28 are connected so that the voltage difference between line 1 and line 3, as well as between the lines 3 and 2 is half the DC link voltage. The positive power connections of switch 8 and the diode 9 are connected to line 1, the negative power connections to line 4. The positive power connections of switch 11 and diode 12 are connected to line 4, the negative power connections to line 2. The control line 5 is connected to the input of the driver circuit 7, whose output is connected to the control input of the switch 8. The control line 6 is connected to the input of the driver circuit 10, whose output is connected to the control input of the switch 11.

In the driver circuits 7 and 10 is also the switch-on delay built-in when the circuit breaker have about a greater switch-off so that it can come to full bridge - the switch on command line 5 comes simultaneously with the switch-off on control line 6 and vice versa - no bridge short circuit ,

Between the lines 4 and 3 is the AC output voltage 29, which is positively equal to half the DC link voltage when switch 8 is closed, the half negative DC link voltage is as long as switch 11 is closed, and is mainly zero when both switches open are.

In Fig. 2, the basic circuit of a full-bridge inverter is shown with phase shift control. The positive terminals of the switches 14 and 20, as well as the diodes 15 and 21 are connected to line 1. The negative terminals of the switches 17 and 23 and the diodes 18 and 24 are connected to line 2. The positively counted output of the inverter is line 4, to which the negative terminals of switch 14 and diode 15 and the positive terminals of switch 17 and diode 18 are connected. The negatively counted output of the inverter forms line 3 which connects the negative terminals of switch 20 and diode 21 and the positive terminals of switch 23 and diode 24. The output AC voltage 29 is applied between the lines 4 and 3.

The control input of switch 14 is connected to the output of driver circuit 16. At the input of the driver circuit 16, the control line 5 is connected. Switch 17 is driven by driver 19. The input of the driver 19 is connected to the output of an inverter 51 whose input is also connected to line 5. The control input of switch 20 is connected to the output of driver circuit 22. At the input of the driver circuit 22, the control line 6 is connected. Switch 23 is driven by driver 25. The input of the driver 25 is connected to the output of the inverter 52, the input of which is also connected to line 6.

The signals on the control lines 5 and 6 are square-wave voltages with a duty cycle of 50% in the steady state. The necessary switch-on delay is realized in the driver circuits. The signal on the control line 5 leads the signal on control line 6 ahead. The signal on line 5 controls the leading bridge branch 14, 17 and the signal on line 6 controls the trailing bridge branch 20, 23.

The circuit breakers 14, 17, 20, 23, the diodes 15, 18, 21, 24 are connected in anti-parallel because the common circuit breaker in the on state can only lead in the direction of the positive to negative power connection current.

By closing the switches 14 and 23, the positive DC link voltage is applied to the output, by closing the switches 17 and 20, the negative. The width of the positive and negative pulses of the output AC voltage 29 results from the phase shift of the signals 5 and 6, as well as the duration of the intermediate freewheeling phase switches 14 and 20 or switches 17 and 23 are simultaneously closed and open.

Fig. 3 shows the process steps in the DC-DC conversion according to the method described in the published patent application DE 196 34 713 A1. The power rectifier 32 is connected to the input side of the network 31, its positive output is connected to line 1 and its negative output to line 2. The DC link capacitor is on the one hand connected to line 1, on the other hand connected to line 2. Line 1 and 2 are the supply lines of the inverter 26, at the output, formed by the lines 4 and 3, the primary side of the power transformer 30 is connected. The pulse widths of the output AC voltage 29 is determined by the signals on the control lines 5 and 6. The secondary side of the transformer 30 is connected to the input of the secondary rectifier 33, at whose output the load 34 is connected.

The load voltage is detected by the voltage measuring device 35 and supplied to the controller 41 with the lines 36. On line 38, the controller 41 receives the actual value of the load current. The controller 41 compares the current actual value on line 38 with the current setpoint on line 39 or the load voltage on line 36 with the voltage setpoint on line 40 and regulates with its output voltage on line 42 corresponding to a certain pulse width of the positive and negative pulses on transformer 30. the power flow. The controller 41 is connected on the output side by line 42 to the input of the pre-filter 83, whose output is connected via line 82 to the input of the pulse width modulator 43. At the output of the pulse width modulator 43, the control lines 5 and 6 of the inverter 26 are connected.

In the current state of the art, the pre-filter 83 applies to its output on line 82 a value which corresponds to only a part of the change at its input on line 42, so that the pulse width modulator 43 generates control signals 5 and 6 for the inverter, so that any changes in the controller output on line 42, the power transformer is likely not saturated, or a maximum permissible transformer magnetization is not exceeded. The pre-filter 83 thus fulfills its function of filtering out the harmonic and subharmonic oscillations of the switching frequency of the inverter possibly contained in the desired value signal 42, which would lead to a steady increase in the transformer DC magnetization. Without prefilter 83 and without further measures to prevent dangerously recurrent setpoint changes, e.g. By reducing the system dynamics, for example by means of the pre-filtering method discussed, the dangerous transformer short-circuit due to the saturation of its core, even with a significantly oversized transformer would only just adjust a little later.

In Fig. 4 are compared to the prior art in Fig. 3, the control lines 5 and 6 shot to the output of the operating method according to the invention device 40 whose signal inputs via the lines 45 and 46 to the outputs of the pulse / 39 Austrian Patent Office AT505 507 B1 2010-03-15 wide modulator 43 are connected. Two further inputs of the device 40 are connected via the lines 47 and 48 to the secondary side of the voltage converter 49, whose primary side is connected to the output lines 3 and 4 of the inverter 13.

Fig. 5 shows the schematic diagram of the device 40. This consists of the integrator 73, a circuit part which sets the critical values of the transformer magnetization in the positive and negative directions on the lines 55 and 56, the comparators 63, 64 and a logic circuit 78 or 79.

The fed-back transformer voltage 72 is supplied to the input of the integrator 73 with the lines 47 and 48. Line 62 connects the output of integrator 73 to the negative input of comparator 63 and to the positive input of comparator 64. The positive input of comparator 63 is connected to line 55, at which the positive critical value of the magnetizing current is tapped. The also fixed potential on line 56, which is connected to the negative input of the comparator 64, determines the negative critical value of the transformer magnetization.

Line 80 from the output of the comparator 63, line 81 from the output of the comparator 64, and the lines 45 and 4 6 of the outputs of the pulse width modulator 43 are connected to the inputs of a logic circuit 78 or 79, the control signals 45 and 46 at their outputs on lines 5, and 6 are turned on as long as the voltages on lines 80 and 81 indicate that the magnetization of transformer 30 is within allowed limits set on lines 55 and 56.

Logic circuit 78 or 79 passes the signals 45 and 46 of the pulse width modulator 43, which are predetermined due to the load of the transformer 30 by the application process, unchanged on the control lines 5 and 6 of the inverter 13 or 26, the alternating DC voltage alternately determined by the application process in the positive and negative direction to the primary winding of transformer 30, unless the removable on line 62, of integrator 73 of the magnetization of transformer 30 and the parallel-connected voltage converter 4 9 mapped magnetization signal the critical value in has reached positive or negative direction.

In the case of the inverter 13, logic circuit 78 outputs to the control pulse on line 45 on line 5 a correspondingly shortened control pulse when the magnetization signal has reached the positive critical value on line 55 and has addressed comparator 63. The control pulse on line 46 on line 6 is truncated when comparator 64 determines that the magnetization signal from transformer 30 has reached its negative critical value set on line 56.

When Vollbrückenkonverter the capacitors 27, 28 are also replaced by circuit breakers. In conventional PWM control, the switch built in instead of the capacitor 27 is switched on and off at the same time as the switch 11 and the switch at the location of the capacitor 28 is actuated together with the switch 8. Unlike the Flalbbrücken inverters now the full DC link voltage is placed in the positive or negative direction of the transformer 30 when switching a pair of switches. Again, logic circuit 78 can be used unchanged.

FIG. 9 shows an example of a logic circuit 79 for the full-bridge inverter with phase shift control 26 in FIG. The logic circuit 78 is included in FIG.

FIG. 6 shows an embodiment of the device 40 operating according to method claim 1 with a logic circuit 78 for the half-bridge balanced converter and the full-bridge balanced converter with PWM control.

Device 40 is powered by voltage 74, for example at 15 volts. The magnetization limits, as well as the reference potential for the magnetization signal are determined by means of the series connection of the same sized resistors 221, 54 with the Zener diodes 222, 53. Resistor 221 is connected to the positive electronics supply 74. Line 55 connects its second terminal to the input of Zener diode 222 and the positive differential input of comparator 63. Line 57 connects the output of Zener diode 222 to the input of Zener diode 53 and the positive differential input of operational amplifier 71. Line 56 connects the output of Zener diode 53 with the resistor 54 and the negative differential input of the comparator 64. The second terminal of the resistor 54 is connected to the electronics ground 77. The zener voltage of the diodes 222 and 53 is for example 1.8 volts. Operational amplifier 71 buffers the zero potential for the magnetization signal present on line 48. The potential of line 55 is e.g. 1.8 volts above the reference potential of line 48, the potential on line 56 is 1.8 volts below.

Integrator 73 is exemplified as a reverse integrator consisting of operational amplifier 61, resistor 58 and capacitor 59, at the input of which the voltage 72, which is proportional to the negative voltage to transformer 30, is fed back, so that the voltage at the integrator output the actual course the magnetization in transformer 30 follows.

The positive terminal of the primary side of the voltage converter 49 is connected to line 4, the negative primary terminal is connected to line 3, so that at the primary side of the voltage converter 4 9, the inverter output voltage or the primary voltage of the power transformer 30 is applied. Voltage transformer 49 is coupled such that a positive primary voltage pulse in the counting direction 29, relative to the potential of line 48, produces a negative voltage pulse in the counting direction 72 at the integrator input on line 47.

On line 4 8, the positive terminal of the secondary side of the voltage converter 49, the output and the negative differential input of the operational amplifier 71, and the positive differential input of the operational amplifier 61 are connected. Line 47 connects the negative terminal of the secondary side of the voltage converter 49 with resistor 58, the further terminal of line 60 is connected to a terminal of the integration capacitor 59 and the negative differential input of the operational amplifier 61. The second terminal of the capacitor 59 is connected to line 62, which is supplied by the output of the operational amplifier 61. The magnetization signal formed at the output of the operational amplifier 61 is further supplied from the line 62 to the negative differential input of the comparator 63 and the positive differential input of the comparator 64.

By virtue of voltage 72, a current flows through resistor 58 and on through capacitor 59, so that there is a voltage on line 62 which follows the integral of voltage 72 multiplied by -1 or the profile of the time integral of transformer voltage 29. The outputs of the comparators 63, 64 are HIGH as the voltage on line 62 moves within the limits defined by lines 55, 56. When the potential on line 55 is exceeded, comparator 63 responds and the signal on line 80 goes low. If the potential on line 56 is undershot when a negative pulse to transformer 30 is applied, comparator 64 generates a LOW signal on line 81.

The signals on the lines 80, 81 and the control signals on the lines 45, 46 are supplied to the logic circuit 78, at whose outputs the control lines 5, 6 are connected for the switches 8 and 11. The logic circuit 78 consists of the inverters 67, 68, the negative edge-triggered RS flip-flops 65, 66, and two AND gates 69, 70.

The reset input of flip-flop 65 is connected via line 80 to the output of the comparator 63. The output of the FF 65 is connected via line 75 to an input of the AND gate 69, whose second input is connected to line 45. The input of flip-flop 65 is connected to the output of the signal inverter 67 whose input is connected to line 46.

The reset input of flip-flop 66 is connected via line 81 to the output of the comparator 64, its Seteingang to the output of the signal inverter 68 and its output via line 76 to an input of the AND gate 70, the second input to line 46 / 39 Austrian Patent Office AT505 507 B1 2010-03-15 is connected. The input of the inverter 68 is connected to line 45.

The lines 45 and 46 are connected to the outputs of the pulse width modulator 43. The pulse width modulator 43 generates from the set point 42 required by the application process the signal 45 for the upper switch 8 which determines the positive pulse duration at the power transformer 30 and the signal 46 for the lower switch 11 of the inverter 13 (Figure 1), which determines the negative pulse duration at the power transformer 30.

During the turn-on state of switch 8 (FIG. 11), the control signal on line 45 (46) may be responsive to comparator 63 (64). In this case, flip-flop 65 (66) is reset, line 75 (76) goes low, and AND gate 69 (70) takes the voltage signal from control line 5 (6), thereby interrupting current flow through switch 8 (11) positive (negative) voltage pulse to transformer 30 is terminated prematurely. The reset pulse on line 80 (81) may be very short. However, the output of flip-flop 65 (66) connected to line 75 (76) remains LOW until flip-flop 65 (66) is reset. This is done only by the following switch-on command for switch 11 (8) on line 46 (45), whereby the premature restart of switch 8 (11) is reliably prevented.

The voltage divider 221, 222, 53, 54 generates the upper integration limit on line 55, the lower integration limit on line 56, and the mid-potential on line 57 which is buffered by operational amplifier 71 and is reliably applied on line 48. Resistor 58, capacitor 59 and operational amplifier 61 form the inverting integrator 73, which integrates the voltage 72, an image of the inverted transformer voltage 29.

When the output on line 62 moves within the limits imposed by lines 55 and 56, the outputs of comparators 63 and 64 are HIGH. The outputs of the flip-flops 65 and 66 are then also high, especially since they are continuously set by the positive edges or turn-on commands of the control signals 45 and 46. In this case, the control signals 45 appears unchanged at the output of the AND gate 69 on line 5 and the control signal 4 6 unchanged at the output of the AND gate 70 which is connected to line 6.

The comparator 63 responds or its output becomes LOW when a positive on-command on line 45 is too long, and comparator 64 can only on a negative pulse of the transformer voltage 29 and during the turn-on command on line 4 speak to. Due to the demagnetization phase following each turn-off operation in the inverter, see Fig. 7, the output pulses of the comparators 63 and 64 are very short, so they are extended by the RS flip-flops 65 and 66 until the turn-on of the other switch. If comparator 63 responds, flip-flop 65 is reset and its output connected to line 75 goes low, whereby AND gate 69 removes turn-on signal 45 from line 5. If comparator 64 responds, then the turn-on signal of line 46 at the output of AND gate 7 0 on line 6 is taken back via line 76.

In Fig. 7, the function of the half-bridge inverter 13 is shown in Fig. 1 with inventive control and logic circuit of FIG. 6 by the diagrams 84 to 92.

Diagram 84 shows the operation of the pulse width modulator 43, which generates, for example, two ramp signals 93 and 94 offset by 180 °. Furthermore, in plot 84, the setpoint voltage 95 is plotted on its input line 42, which is determined by the process in the region of application of the inverter 13.

From the diagrams 85 and 86, the control signals on the lines 45 and 46 with the switching states 96 and 97 of the switches 8 and 11 can be seen, wherein the diagram 85, the switch states 96, 97 of the switch 8 and diagram 86, the switch states 96, 97 of the switch 11 represents.

In diagram 87, the voltage 29 of the primary winding of the transformer 30 connected to the lines 4 and 3 is shown, and in diagram 88 the time course of the magnetization of the transformer 30 and / or of the magnetization signal on line 62.

If the inverter 13 is put into operation, generates modulator 43 from the regulator output voltage 95, the control signal for switch 8, the device of the invention 40 in Fig. 6 of line 45 on line 5 turns on, when voltage 98 and thus the magnetic flux in the transformer core within the set limits. Similarly, device 40 forwards the switch states 96, 97 for switch 11 of line 46 on line 6. Closes on the line 5 switch 8, the voltage of capacitor 27 is in the positive counting direction of voltage 29 at the primary winding of transformer 30. When switch 11 is closed, the voltage of capacitor 28 is in the negative counting direction on the primary side of the power transformer. The capacitors 27, 28 charge during commissioning to half the DC link voltage, which is present between the lines 1 and 2.

Due to the alternately switching on of the switches 8, 11, the primary voltage 29 is applied to the primary side of the transformer 30, which is transmitted and subsequently connected e.g. is rectified again via the secondary rectifier 33 and supplies the load 34 with power and voltage.

As can be seen from the diagrams 85, 86, modulator 43 sets the switch-on time of switch 8 with the start of the ramp signal 93 and the switch-on time of switch 11 with the start of the ramp signal 94. The switch-off time for switch 8 determines modulator 43 at equal voltage of ramp signal 93 and regulator output voltage 95, the switch-off for switch 11 is given at voltage equality of the signals 94 and 95. In this way, modulator 43 determines the turn-on durations 99 for switches 8 and the turn-on durations 100 for switches 11.

At the zero voltage point of the ramp signal 93 at a time 101 modulator 43 controls the switch 8, whereby the transformer 30, as shown in diagram 87 delayed by the driver and switch times delayed at time 102, a positive voltage in the counting direction of voltage 29 , which corresponds to half the DC link voltage, is placed. At time 103, voltage equality occurs between ramp signal 93 and regulator output voltage 95, whereby modulator 43 takes the voltage signal from control line 45 and, somewhat delayed at time 104, the current flow through switch 8 is interrupted.

As can be seen from the synopsis of the diagrams 87, 88, by applying a voltage to the transformer 30, its core is magnetized, i. It forms through the primary winding of transformer 30 from a magnetizing current, the voltage proportional linear increase or decrease. The storage of the magnetizing current, or intervals in which the transformer voltage is zero, can only occur if a load current has already formed. The load is switched on at a later time 108 and inverter or transformer 30 are initially idle.

By applying a positive voltage to the transformer 30, i. the switch 8 is in the conductive state, the level of the negative magnetization of the transformer 30 is reduced or reversed during the application of the positive voltage according to a linear function from the time 102. At time 104, the magnetizing current in the primary winding of transformer 30 due to the previously controlled switch 8, the amplitude 105. The magnetizing current, previously fed by capacitor 27, commutes during turn-off of switch 8 into diode 12, whereby capacitor 28 of the primary side of transformer 30 is in anti-parallel and transformer 30 is against the voltage on capacitor 28, which is half the intermediate circuit voltage demagnetized, ie the negative voltage is applied to the transformer 30 until the magnetizing current has decreased linearly to the value zero, which is reached at a time 108. At the zero voltage point of the ramp signal 94 at a time 106, modulator 43 drives the switch 11, thereby delaying the transformer 30 to drive and switch cycle times, one at a time in the count direction of voltage 29 negative voltage corresponding to half the intermediate circuit voltage is placed. At time 107, voltage equality occurs between ramp signal 94 and regulator output voltage 95, whereby modulator 43, as shown in diagram 86, takes the voltage signal from control line 46 and, somewhat delayed, the current flow through switch 11, if present, is interrupted.

As can be seen from the graphs 87 and 88, the duration of the negative voltage pulse on transformer 30 due to the magnetizing current 98 through diode 12 results in the illustrated case.

At the time 108, the transformer 30 is demagnetized, voltage 29 breaks down to the value zero together and diode 12 appears a reverse voltage, which corresponds to half the DC link voltage. After time 108 and before time 109, the load 34 is now switched on.

At time 109, the pulse width modulator 43 outputs on line 45 a switch-on state 97 for switch 8, which turns on at time 110 and sets half the DC link voltage in the positive direction to the transformer 30. Modulator 43 only takes the switch-on state 97 for switch 8 back to time 114, but the maximum permissible magnetization is already reached at time 111. The output of comparator 63 becomes LOW, as a result of which the output of flip-flop 65 is also connected to line 75.

The magnetization increases until time 112, in which switch 8 actually turns off and the current in diode 12 commutes still around B55 * 4 * tv / T over the line 55 set limit on the actual occurring maximum positive magnetization with the amplitude 116 on. Computationally, the maximum duration of time which can pass between the switch-off time point 111 of the control signal and the actual switch-off of switch 8 at time 112 can be used for tv.

As a result of the voltage at the transformer 30, which is now negative from time 112, the current transmitted to the secondary side decreases rapidly to zero according to a linear function whose slope is determined by the leakage inductance of transformer 30. On the secondary side, the load current is now no longer supplied by the primary side, but is driven by the inductive load and / or a series-connected to the load smoothing inductance, whereby the secondary rectifier is short-circuited. Therefore, a further commutation of the magnetizing current to the secondary side begins at the same time, which is completed just after the start of the time interval 112,113, when the magnetizing current makes up only a fraction of the load current. In Zeitindervall 112, 113 occurs due to the negative voltage 29, a partial demagnetization of transformer 30. If the leakage inductance of transformer 30, which was charged up to the time 112 to the load current, demagnetized at time 113 and diode 12 is no longer current flowing breaks the Transformer voltage together. The remaining magnetization at the value 117 stores transformer 30 on the secondary side.

As can be further seen from diagram 88, the voltage on line 62 drops below the value on line 55 in the time interval 112, 113, which is why the LOW pulse of comparator 63 has to be extended.

Diagram 89 shows the output signal of flip-flop 65 on line 75. Flip-flop 65 is reset by the falling edge of the LOW pulse on line 80, and only at turn-on time 115 from the control signal on line 46 for switch 11, ie until the end of maximum pulse width of switch 8, again set.

Diagram 90 shows the control signal for switch 8.

The switching state is identical in the time interval 101, 111 with the control signal on line 45 in diagram 85. From time 111 it is due to the signal on line 75 to 12/39 Austrian Patent Office AT505 507 B1 2010-03-15

End of the theoretically possible maximum duty cycle at time 115 taken from the line 5.

A delay time after time 115, switch 11 becomes conductive. Modulator 43 outputs a large duty cycle, at the end of which, after a further delay time until switch 11 is turned off at time 118, the magnetization in diagram 88 has the negative amplitude 119. Due to the change from set point signal 95, modulator 43 outputs a small duty cycle to transformer 30 for the now following positive pulse, so that transformer 30 already switches to negative at time 120 in which modulator 43 turns on switch 11 and applies a negative voltage pulse to transformer 30 Value 121 is biased and in this state does not tolerate a long negative voltage pulse. After switching through switch 11 to time 122, the magnetization of transformer 30 continues to increase in the negative direction, so that already at time 122, the negative magnetization limit set on line 56 is reached, comparator 64 responds and flip-flop 66 resets.

Diagram 91 shows the output of flip-flop 66 on line 76, and in diagram 92 the control signal for switch 11 on line 6 is shown. Flip-flop 66 is set only by the subsequent turn-on command for switch 8 at time 123, whereby the control signal for switch 11 is taken at time 122 to the end of the maximum duty cycle at time 123 from the control line 6.

The switching states of the switches 8, 11 before and after the time intervals 112, 115 and 122, 123 correspond with their control signals generated by modulator 43 on the lines 45, 46. In the period between the times 111 and 115 and 122 123, the control signals taken on the lines 45 and 46 of the lines 5 and 6, so that the magnetization of transformer 30, the maximum value in the positive direction, which is determined by the voltage on line 55 and the maximum value in the negative direction, by the Voltage on line 56 is determined, does not exceed.

The signal curve in diagram 88 corresponds to the integrator output voltage on line 62 and the course of the induction B or the magnetic flux Φ in the transformer core to which the magnetizing current is proportional. For the dimensioning of the transformer core its maximum allowable induction BMax is decisive, which is determined by the induction value B55, which corresponds to the voltage on line 55.

8 shows the mutually corresponding courses of transformer magnetization and magnetization signal for a transformer connected to inverter 13 or 26 between times 110 and 112 for a minimum operating voltage UZk, min / ramp 150 and ramp 151 at, for example, twice the operating voltage Uzk, max · = 2 * Uzk, min. when using device 40 in FIG. 6 with logic circuit 7 8 or 79, as well as a dash-dotted registered corrected curve 159 of the magnetization signal, so that the maximum core induction at twice the operating voltage is not exceeded.

The estimated states on the control lines 5, 6 occur later than the positive or negative pulse of the transformer primary voltage 29 by the delay time tv. The integration speed or the voltage rise on line 62 results from the current with which capacitor C is charged or discharged and is to be adjusted by resistor 58 Rint such that during the maximum pulse width of the positive and negative pulses of transformer voltage 29 of approximately the duration of half the period of the switching frequency k / T / 2, k-1 < 1, in which transformer 30 is re-magnetized from -BMAx to + BMax and u72 is present at the amplitude u72 at the integrator input, the output voltage of the integrator on line 62 changes from the negative to the positive maximum value, ie 2 * UMax. This condition applies to push-pull inverters 13 and 26, where ^ can advantageously be assumed to be 1 because the delay time does not change the pulse width.

At a minimum operating voltage, half of the maximum duty cycle of T / 4 elapses between times 110 and 112, and from zero to the maximum value of 13/39 in the transformer 30

Austrian Patent Office AT505 507B1 2010-03-15 netisiert. Equation 1 therefore applies: [00117] dB / dt = 4 * BMax / T, and

Eq. 1 [00118] du62 / dt = 4 * Umax / T = U72 / (Rint * Cint) In the delay time tv 111,112, the induction in transformer 30 increases from the value 152 B55 at time 111 according to equation 1 to the maximum value 116 BMAx which is reached at time 112.

[00120] Bmax = B55 + k * BMAXj with k = 4 * tv / T

Eq. 2 Analogously, the positive limiting voltage on line 55 is calculated so that Umax is not exceeded by u62, according to Equation 2 to [00122] U55 = Umax * (1-k) Equation 3 in Equation 1 and after R | Nt solved gives: Rint = (1-k) * U72 * T / (4 * U55 * CINT)

Eq. 3

Eq. 4 [00125] At e.g. U55 = 1.8V, C! Nt = 1nF, U72 = 2V, T = 32ps and tv = 1ps R | NT is calculated as Rint = 7,8 kn. For double DC link voltage, k2 = 2, the curve 151 is entered in FIG. 8. The maximum magnetization 116 is reached at time 155, which lies exactly in the middle between times 110, in which switch 8 turns on, and time 112, in which it switches off again at minimum DC link voltage. Device 40 now has to ensure that the control signal for switch 8 is already taken back at time 154, the delay time tv before time 155. The ratios shown correspond to the above realistic numerical example. If the inverter is now in a wide input voltage range Uzk.min < Uzk < k2 * UZK, min > k2 > l, it should be noted that the difference BMax - B55 is reduced by the factor k2 to [00128] Bmax B55 2 ~ k2 * k * BMAx Eq. 5 [00129] enlarged. Transformer 30 would switch off without further precaution until time 157, because the integrator output voltage in device 40 reaches 152 only at time 156. The core of transformer 30 would have to be designed for the maximum value 158 BMax, 2, which is calculated as ΒΜΑχ, 2 = BMAx - B55,2 + B55. The factor ÜD by which the core cross-section must be increased, ÜD = Βμαχ, ς / Βμαχ '1 Eq. 6 yields equations 2 and 5 in this case to [00133] UD = k (k2-1). Eq. In the case shown, when the supply voltage is doubled, ÜD = 12.5%. This oversizing is economically justifiable, whereby push-pull converters can also be used in this field of application. In accordance with the method, for example, the voltage U55 can be more cost-effective than an acceptable overdimensioning of transformer 30 according to [00136] Uö5 | 2 = Umax (1 · k2 * k)

Eq. 8 [00137] are reduced in proportion to the increase in the intermediate circuit voltage, which is particularly easy to implement digitally. For example, starting from magnetization progression 150 with a minimum supply voltage of the inverter, the integration speed of the feedback transformer voltage 72 can be proportional to the increase in the intermediate circuit voltage 35 Uzk by the factor k2, [00138] FIG. are slightly increased relative to the actual increase in magnetization in the core of transformer 30.

In FIG. 8, the profile 159 of the integrator output voltage u62, Korr on line 62 is plotted in the case of the supply of the inverter with double DC link voltage, which differs from the actual magnetization curve 151. Because the voltage value 152 on line 55 was not intervened, the curve 159 increases slightly steeper than the actual magnetization curve 151, so that the value 152 is also reached at the time point 154.

In the following, for this approach, the current IKorr is calculated, which in addition to the current I! Nt = U72 / Rint, which corresponds to the amplitude U72 of the fed-back transformer voltage 72, is to be fed to the integrator 73.

The course of the actual magnetization corresponds to the integration of the curve of Iint, which results from equation 1 with the setting of k from equation 2 to Iint / Cint = k2 * k * UMAx / tv Eq. 9 [00143] is calculated. I | NT is in the time interval 100, 155 exclusively a function of the variable DC link voltage Iint = Ιιντ (Μ, k2 = Uzk.max / Uzk.min- From the slope of U62, corr the required charging current of Cint results from the equation 10th

[00145] (Ikorr + Iint) / Cint = k2 * k * (1-k) Umax / ((1-k2 * k) * tv) Eq. From Equations 9, 10, the nonlinear expression for IKorr / Iint results from Equation 11, [00147] Ikorr / Iint = k * (k2-1) / (1-k2 * k), Eq. [00148] which is represented by the linear expression Ikorr.lin / Iint = k * (k2-1) / (1-k2MAx * k), Eq. 12 [00150] is replaced. With k2 from Equation 2, the correction current Ikorr, lin is calculated as [00151] Ikorr.lin = k * (Uzx - Uzk, MiN) / (ü * RiNT * (1-k2, Max * k)) with ü = N1 / N2, Eq. 13 can also be considered by analog circuit in the simplest way, where ü the transmission ratio of the voltage converter 4 is 9.

Obviously, the linearized expression from Equation 12 is true for k2 = 1, which must be assumed in the current dimensioning of transformer 30 and k2 = k2iMAx, for which the transformer core must be designed.

According to equation 11 Ikorr increases disproportionately with increasing DC link voltage, which is why in the linear approximation in equation 12, which is inexpensive to implement, for intermediate values of the DC link voltage results in a slightly smaller correction current and BMax is slightly exceeded.

In order to calculate the factor ÜD for oversizing, first the value of k2 'at which the largest error occurs is determined.

The error function F is defined in equation 14.

F = (Ikorr Ikorr, lin) / Iint Eq. 14 Since IKOrr is already considerably smaller than I | NT, a small error is to be expected.

The value for k2 'is given by the condition 16. The error function F with the used expressions for Ikorr and Ikorr.lin from the equations 11,12 must be derived after k2 and set to zero. 15/39

Austrian Patent Office AT505 507 B1 2010-03-15

Eq. 15 [00160] dF / dk2 = 0, for k2 = k2 'For small values of k, thermals with higher powers of k can be neglected. This neglect is allowed if condition 16 is satisfied by the law of k in Equation 2.

Eq. 16 The delay time may only make up a fraction of one quarter of the period of the switching frequency. This condition is usually met. As expected, the largest error occurs in the middle of the operating voltage range:

Eq. K2 = (1 * k2, MAX) / 2 [00165] Either the somewhat lower utilization of the transformer 30 in the middle operating voltage range is allowed, or it is designed so that it can also transmit the full power in this range. The transformer is then designed not to be BMax, but to the maximum core inductance BMAX, 2, which then occurs at the operating voltage range limits. If fully compensated, BMAx would appear at the range limits.

[00166] ΒΜΑχ, 2 / ΒΜΑχ = (IINT + Ikorr, lin) / (1 | NT + Ikorr) Eq. For OV from Equation 6, the overdimensioning factor UD is finally calculated using equations 9, 11 and 12 as:

Eq. [00169] ÜD = (1- k2 '* k) 2 / ((1-k) * (1-k2, MAx * k)) - 1 With the exemplary realistic values, which are also shown in FIG is turned off, the value for ÜD becomes ÜD = 1/168 = 0.6%. From a practical point of view, this method allows the operation of the inverter 13, 26 at variable supply voltage compared to the known prefilter method, wherein the core of transformer 30 can advantageously also be designed for the smallest supply voltage. The device 40 required in the process diagram Fig. 5 is shown in Figs. 6.9 executed.

Fig. 9 shows a simple circuit for correcting the magnetization signal with variable DC link voltage according to equation 13. The circuit shown is the input side to the lines 47, 48 and the output side to line 60, that is connected in parallel to the integration resistor 58 Rint in Fig. 6. Furthermore, it is assumed that the equal positive and negative amplitude of the feedback transformer voltage 72 is 2.5 volts with the minimum DC link voltage. This is the zener voltage across diodes 52 and 53 in FIG. 6, respectively, which define the potentials tapped from leads 55 and 56 plus the diode current voltage of diode 162 and 163, respectively.

With line 47 of the circuit, the feedback transformer input voltage u72 = u29 / ü is supplied, the amplitude of which corresponds to half, in the case of the half-bridge inverter, or the full DC link voltage. This is taken into account in the dimensioning of the transformer 30, so that the described conditions occur.

On line 47, the resistors 160, 167 are connected. Line 161 connects the second terminal of resistor 160 to the negative differential input of buffer amplifier 168, the input of diode 162 and the output of diode 163. The output of diode 162 is connected to the output of amplifier 165, which buffers the voltage on line 55 , The input of diode 163 is connected to the output of amplifier 166, to which the voltage of line 56 is loaded.

The transmission ratio ü of the voltage converter 49 is selected so that the diodes 162,163 just do not intervene when the inverter is operated at the minimum intermediate circuit voltage. Advantageously, this eliminates another voltage divider. If a higher operating voltage is applied, the positive pulses of the fed-back trans- 16/39

Austrian Patent Office AT505 507 B1 2010-03-15 diode 163 is clamped to the potential of the line 55 by means of diode 162 and diode 163 connects the output of amplifier 166 to line 161 during the negative pulses, so that the voltage of line 161 of the minimum DC link voltage in positive or negative direction. The voltage on line 161 is available at the output of the amplifier 168 on.

Resistor 167 is connected to the negative differential input of amplifier 164 and one terminal of resistor 169, the second terminal of which is connected to the output of amplifier 164. The positive differential input of the amplifier 164 is connected to line 48. The resistors 167,169 are ideally equal and R! so that at the output of amplifier 164 on line 170, a voltage is present, which corresponds during the positive pulses of the voltage 72 of the current intermediate circuit voltage in the negative direction and during the negative pulses of the voltage 72 of the current intermediate circuit voltage in the positive direction.

The positive differential input of summing amplifier 171 is connected to line 48. The negative differential input is connected to the summing point to which resistors 172, 173 and 174 are connected. The second terminal of resistor 172 is connected to the output of amplifier 168, the second terminal of resistor 173 is connected to the output of amplifier 164 and the second terminal of resistor 174 is connected to the output of summing amplifier 171. The output of the summing amplifier is connected to the resistor 175 Rkorr, whose second connection goes on line 60. The resistors 172, 173 are ideally equal in size, R172 = R * The amplitude Ukorr of the output voltage of the summing amplifier 171 is calculated as: Ukorr = Uzk-Uzk, min) * Ri74 / (Ü * R172) Eq. 20 During the positive pulses of the voltage 72, the positive current Ikorr.lin integrator 73 is additionally supplied, while the negative pulses -Ikorr.lin- [00180] Ikorr.lin = + - (Uzk-Uzk, min) * Ri74 / (Ü * Ri72 * Rkorr) Eq. 21 Equation 13 calculates the resistance Rkorr to:

Eq. Rkorr = R175 = Rint * R3 * (1 _k2 MAx * k) / (k * R2) With the k = 1/8 and k2, MAx = 2 given previously in the numerical example, RKOrr is added

Rkorr = 7 * R * nt * Ri74 / Ri72- In Fig. 11, logic circuit 79 for the full-bridge inverter with phase shift control is shown in Fig. 2. FIG. 10 shows the temporal courses of the essential quantities on the basis of the diagrams 124 to 131.

Diagram 124 shows the ramp signal 132 with ideal linear rise and infinite slope of the falling edge generated by modulator 43. Furthermore, the controller output signal 95 is entered, the modulator 43 is supplied from the controller output on line 42. In the case shown, the regulator output voltage is at its upper limit, which is just below the amplitude of the ramp voltage, because in the case shown for higher DC link voltage of the invention protected transformer, for example, can not transmit the required power.

Diagram 125 shows the switching states 133, 134 output by modulator 43 on the basis of voltage 95 on lead 45 for the leading bridge branch with the switches 14, 17. Diagram 126 shows the switching states 133,134 for the trailing bridge branch output on line 46 with the switches 20, 23. In state 133, switch 17 is closed in the leading branch, switch 14 is open and line 4 is connected via line 2 to the negative pole of the DC voltage supply. In the trailing branch, switch 23 connects line 3 to the negative pole of the DC power supply, and switch 20 is open. State 134 of the leading branch means that the closed switch 14 connects line 4 17/39 Austrian Patent Office AT505 507B1 2010-03-15 with line 1, which is connected to the positive pole of the DC voltage supply and switch 17 is open. In the trailing branch line 3 is connected by switch 20 to the supply line 1 and switch 23 open (Fig. 2).

Modulator 43 generates e.g. the control signal on the leading bridge branch line 45 by specifying the switching timings with the start times of the ramp signal 132. The switching times of the signal on lead 46 for the trailing bridge branch are e.g. determined at equality of the regulator output voltage 95 with the ramp signal 132. In the illustrated case, modulator 43 generates in this way two switching-frequency rectangular voltages with the maximum turn-on times of 50%, wherein the signal on line 4 6 lags the signal on line 45 by nearly 180 °, or half a period of the switching frequency.

At time 135, the leading branch has switched and line 4 is connected to line 1. The trailing branch connects line 3 to supply line 2. The transformer circuit 30 is the DC link voltage in the positive direction and there is a re-magnetization, which would end the control signal on line 46 for the trailing branch after almost half a period of the switching frequency, at time 138 , The nuclear magnetization reaches its critical value, which is fixed on line 55, but already at time 136.

It can be seen that the magnetization of transformer 30 in diagram 127, as well as the transformer primary voltage 29 in diagram 131 relative to that defined by modulator 4 3 on the lines 45, 46, correspond to a lower phase shift, according to which now permanently engaged device 40.

[00190] Diagram 128 shows the output voltage of flip-flop 65 on line 75. Flip-flop 65 is set at time 136, in which the magnetization has reached the positive value set on line 55, and remains set until the end of the maximum pulse width at time 139. Owing to the ORing of the signals on the lines 75 and 46, the control signal for the trailing branch on line 6 already outputs the operating state 134 from time 136.

A delay time later, composed mainly of the drive cycle time and the switching delay time of the power switches, at time 137, in which the trailing branch switches and voltage 29 becomes zero, the magnetization has grown to its positive maximum value and remains until the next changeover time 14 0 of the leading branch stored.

By switching the leading branch, the negative DC link voltage is applied to transformer 30, as shown in diagram 131, and the remagnetization takes place in the negative direction. The critical negative induction value corresponding to the voltage on line 56 is reached at time 141. Comparator 64 responds and resets flip-flop 66 with its output on line 81. Flip-flop 66 is set again only at the end of the maximum duty cycle by the rising edge of the signal on line 45 at time 143. The ANDing of the signals on the lines 46 and 76 causes the operating state 133 is output on line 6 from time 141. At time 144, the leading branch switches, causing the positive intermediate circuit voltage to be applied to transformer 30 again. One period of the switching frequency has passed and the sequence described from time 135 is repeated again.

The operating state 134 on line 46 appears to be advanced by the operation of logic circuit 79 on line 6 for the same amount of time between times 136, 138, and 141, 142, respectively, whereby the positive and negative pulses of voltage 29 is shortened equally, so that the maximum induction in the core of transformer 30 is also not exceeded due to a higher operating voltage and excessive load. If a variable DC link voltage is also considered in device 40, e.g. contains the circuit in Fig. 9, so can transformer 30 to the nominal power of the Austrian patent office AT505 507 B1 2010-03-15

Device are designed.

FIG. 11 shows, by way of example, a logic circuit 79 for the full-bridge inverter with phase-shift control. As can be seen from the diagrams 15, 126, a shortening of the drive phases takes place when the trailing branch switches over prematurely. Circuit 79, for example, only changes the control signal for the trailing bridge branch output by modulator 43 on line 46 with the switches 20, 23. Line 45 is connected to line 5. The control signal for the leading branch is not intervened.

The positive pulse of voltage 29 is shortened by the control signal on line 6 against the signal on line 46 prematurely switches from the operating state 133 to the operating state 134. The OR gate 146 is connected on the input side to the lines 46 and 75, on the output side to line 145. Line 75 is connected to the output of negatively edge-triggered RS flip-flop 65, which is consistently reset when the leading branch control signal on line 45 transitions from operating state 134 to operating state 133. In FIG. 10, this occurs at the time 139, whereby, after the delay time tv at the time 140, the intermediate circuit voltage is applied to the transformer 30 in the negative direction. Time 139 marks the end of the theoretically achievable length of the positive pulse of primary voltage 29. Flip-flop 65 is set by the output of comparator 63 on line 80. Comparator 63 can only respond within a positive voltage pulse 29, while line 46 has the operating state 133 (LOW). Only when comparator 63 has responded, for example at time 136 and line 75 has the operating state 134, does gate 146 output on line 145 against the signal on line 4 6 the operating state 134 (HIGH). Line 145 and line 76 are connected to the input of AND gate 147, whose output is routed to control line 6. During a positive voltage pulse 29, line 46 has the operating state 133, line 76 is in operating state 134, so that the premature change of the operating state from 133 to 134 on line 75 compared to line 46 to the lines 145 and 6 is turned on. The positive pulse is removed from time 137 until start time 140 of the negative voltage pulse from transformer 30, so that it does not saturate in the positive direction.

Line 76 is connected to the output of the negative edge-triggered RS flip-flop 66. Line 149 connects the output of inverter 148 to the SET input of flip-flop 66. The input of inverter 148 is connected to line 45. Flip-flop 66 is constantly set by the signal on line 45 at about time 143 when it transitions from operating state 133 to state 134 and a positive pulse of primary voltage 29 is started. The negative pulse of voltage 29 will shorten a delay time after time 141 in which comparator 64 responds and flip-flop 66 is reset from the signal on line 81 until time 144, a delay time after time 143. This in turn can only happen during a negative voltage pulse 29, while the lines 46,145 have the operating state 134. The signal on line 6, together with the signal on line 76, then prematurely switches at time 141 opposite to the signal on lines 4 6 and 145 from operating state 134 to state 133. The negative intermediate circuit voltage becomes the delay time after time 141 until the start time 144 of FIG positive impulse taken from transformer 30 so that it does not saturate in the negative direction.

Now, in this method when operating the inverter to a substantially constant intermediate circuit voltage and constant delay time, in particular in the full-bridge inverter with phase shift control, can be dispensed with the feedback. In FIG. 12, the voltage converter 4 9 is omitted with respect to FIG. 4 because induction limiting device 50 predicts the course of the magnetizing current directly from the signals 5 and 6. This method requires a sufficient constancy of the delay time tv, so that the operating states 96, 97 of the half-bridge inverter and 133.134 of the full-bridge inverter with phase shift control, or the duration of the positive and negative pulse of the primary voltage 2 9 within a period of the switching frequency sufficiently accurate with the duration of Operating conditions 96, 97, and 133,134 on the tax 19/39 Austrian Patent Office AT505 507B1 2010-03-15 lines 5, 6 matches.

FIG. 13 shows the circuit diagram of a device 50 operating according to this principle for the half-bridge inverter in FIG. 1. Compared to device 40 in FIG. 5, the fed-back transformer voltage 72 present between the input lines 47, 48 of the integrator 73 is detected by means of a Signals on the control lines 5, 6 for the circuit breaker 8,11 replicated voltage 199 replaced.

Line 47 connects the integrator input to the output of switch 178 and the input of switch 180. Input of switch 178 is connected to line 55 at which the positive limit voltage is present. The output of switch 180 is connected to line 56 at which the negative limit voltage is present. The voltages between line 55 and line 48, and between line 48 and line 56 are the same size, see Fig. 6.

The control signal on line 5 for power switch 8 is supplied to the input of the controller 177 for switch 178. The input of the control device 17 9 for switch 180 is connected to control line 6 for circuit breaker 11.

When the operating state 97 for switch 8 is output on line 5, switch 180 is actuated and the voltage on line 56 is applied to the input of the integrator, line 47, whereupon, according to the closed switch 8, the magnetization of transformer 30 increases. and, due to the closed switch 180, also the magnetization signal on line 62. If line 6 is in operating state 97, power switch 11 and switch 178 are engaged, whereupon the magnetization of transformer 30 and the voltage on line 62 increase in the negative direction.

In circuit 197 of FIG. 5, which is likewise connected on the input side to the lines 45, 46, 80, 81 and supplies the output of the control lines 5, 6, logic circuit 78 in FIG. 6 is to be used.

In contrast to the known prefilter method, an arbitrary reduction of the pulse width of voltage 29 is permissible, wherein the magnetization in transformer 30 has a DC component at the reduced pulse width, which decays in time. Now, the theoretical case can occur that after many switching periods, the controller 41 suddenly again requires a large pulse width. If, for example, the transformer 30 was magnetized in the negative direction, the increase in the following positive pulse to almost the full pulse width is possible in contrast to the known prefilter method. However, if the magnetization at this time has already subsided to a large extent, then, as in the known methods, only the enlargement to half the maximum pulse width is permissible for the time being, otherwise the transformer 30 would have to be designed for twice the power for this theoretical case. It is therefore proposed to take demagnetizing effects, such as the primary-side or secondary-side linear demagnetization into consideration against the valve-line voltages in the freewheeling intervals and / or the exponential decay of the direct magnetization with a large time constant, according to the sum of the resistances in the respective circuit.

Fig. 14 shows an example of such an extended integrator circuit 73 in Fig. 5 for the full-bridge converter with phase-shift control in Fig. 2. The circuit is explained with reference to the diagrams 200 to 210 in Fig. 15.

Induction limiting device 50 in FIG. 5 therefore consists of limiting device 197, in which now the logic circuit 79 in FIG. 11 is to be inserted and integrator 73 from FIG. 14.

Circuit 197, the magnetization signal on line 62, and on line 45, the leading branch control signal, the switches 14,17, and on line 46, the trailing branch control signal, switches 20 and 23 is supplied. The control lines 5, 6 connected to the outputs of circuit 197 are fed back to the input of the integrator circuit 73 in FIG. 14 or control integrator 73 in the drive phases by means of the electronic switches 178, 180. FIG. 15 shows the essential waveforms within a period of the switching frequency of the inverter in FIG. 2 for a steady state operation. Diagram 200 shows the leading branch control signal on lines 5, 45 connecting logic circuit 79. Diagram 201 shows the control signal for the trailing branch whose phase shift corresponds to the value at the controller output. The transformer magnetization is not critical and circuit 197 is not engaged, the signal on line 46 is turned on on line 6.

One input of the XOR gate 181 is connected to line 5, the other to line 6. Line 182 connects one input of AND gate 183 and one input of AND gate 184 to the output of XOR gate 181. The other input of gate 183 is on line 5, the other input of gate 184 is connected to line 6. Line 185 connects the output of gate 183 to the input of the control circuit 179 for switch 180, which is connected on the output side to line 56 and on the input side to line 47. Line 186 connects the output of gate 184 to the input of the control circuit 177 for switch 178, which is connected on the output side to line 47 and on the input side to line 55. For the transistors 178, 180, because of the accuracy and because the control circuits 177, 178 are also very simple, it is possible to use paired p and n transistors.

Diagram 202 shows, according to the control signals on lines 5, 6, the voltage 199 applied to the integrator input on line 47 in the negative counting direction. It can be seen that the gates 181, 183 and 184 serve not to simultaneously turn on both switches 178, 180 from time 219 to 220 and thus to apply the potential of line 48 to the integrator input, line 47. Diagram 203 shows the output of the XOR gate on line 182. Diagram 204 shows the output of gate 183 on line 185 which drives switch 180 and generates the negative pulse of voltage 199 while on power transformer 30 - shifted only by a delay time positive pulse of voltage 29 is applied. Due to the inverting operational amplifier circuit 58, 59, 61, 48, the magnetization signal rises on line 62, corresponding to the actual magnetization of transformer 30. Diagram 205 shows the control pulse on line 186 for switch 178 which is closed when inverter 26 applies negative DC link voltage to transformer 30 and the transformer magnetization and accordingly the output voltage of integrator 73 between lines 62, 48 decreases.

Furthermore, it can be seen that voltage 199 has no delay time with respect to the control signals and its amplitude U55 minus the switch-current voltage UF of the switch is 178 or 180. The connected to the lines 47, 60 integration resistor 58 R | Nt is therefore calculated from Eq. 1 with k-1 = 1, Umax = U55 and U72 = U55-UF to [00211] R, nt = T * (U55-Uf) / (4 * U55 * C | Nt) Eq. 24 [00212] With the exemplary values T = 3-2ps, U55 = 1.8V, C | NT = 1nF and UF = 0.3V, R, nt is calculated to RTNt s 6.7kQ.

The magnetization of transformer 30 is determined during the drive phases by driving the switches 178, 180. Two further switches 187, 188 are engaged during the freewheeling intervals.

The embodiment of the integrator 73 in FIG. 14 has another input connected to line 193 which is connected to line 55 either via switch 187 or to line 56 via switch 188, or remains open during the drive phase. With resistor 194 RENt, which is connected on the one hand to line 193 and on the other hand to line 60, the linear demagnetization of transformer 30 is considered in the freewheeling phases against the valve voltage voltages UVF. UVF sets each, whether via switch 14 and diode 21 or switch 20 and diode 15 in the upper freewheel via supply line 1 or in the freewheeling phases via supply line 2, in which either 21/39

Austrian Patent Office AT505 507B1 2010-03-15

Switch 17 and diode 24 or switch 23 and diode 18 are energized, from the sum of a diode and a Schalterflußspannung together. The direction in which integrator 73 has to integrate its input on line 193 depends solely on the instantaneous magnetization of transformer 30 at the end of the drive phase, or at the beginning of the freewheel phase, because it counteracts the cause.

Line 62 is therefore further routed to the negative differential input of comparator 213 whose positive differential input is connected to line 48. The output of comparator 213 routed on line 216 is HIGH when transformer 30 is negatively magnetized, or the integrator output voltage of line 62 on line 48 is negative and LOW at positive magnetization. Furthermore, an input of the AND gate 192 and the input of the inverter 214 is connected to line 216. Line 215 connects the output of inverter 214 to an input of AND gate 191. The signal on line 215 is shown in diagram 207. It indicates the magnetization state of transformer 30. The other inputs of the AND gates 191, 192 are connected to line 217, which is supplied by the output of the inverter 218. At the input of inverter 218, the signal is on line 182 in diagram 203.

Diagram 206 shows the signal on line 217 which is HIGH during the freewheeling phases and LOW during the drive phases. If the transformer magnetization is now negative, the AND gate 192 switches the freewheel signal of line 217 to its output on line 195, as shown in diagram 209. Switch 188 is turned on by controller 190 and the negative voltage of line 56 is applied to the integrator input on line 193. With negative magnetization of transformer 30, the integration takes place in the positive direction.

When transformer 30 is positively magnetized, the flywheel signal from line 217 is fed from AND gate 191 to line 196, whereupon controller 189 closes switch 187 and the positive voltage from line 55 is applied to the input on line 193, whereupon This input is an integration in the negative direction. Diagram 208 shows the control signal on line 196 for integration in the negative direction.

When the magnetization signal crosses the zero potential within a freewheeling interval coming from positive or negative direction, comparator 213 reverses the direction of integration, whereby the magnetization signal is kept at zero or integrator 73 is stopped until the beginning of the next freewheeling phase over the following drive phase as it also corresponds to the actual conditions in transformer 30.

Diagram 210 shows the magnetization of the transformer 30 or the magnetization largely corresponding course of the magnetization signal, which simulates the magnetization in the drive phases and the demagnetization in the freewheeling phases.

Dash-dotted another course 212 of the magnetization is registered, which moves only in the negative region. Comparator 213 does not switch, as shown in broken lines in Diagram 7. The freewheel signal in diagram 206 continues to be routed on line 195, as shown by the dot-dash line in diagram 209. Therefore, in the freewheeling interval from time 119 to 120, curve 212 has a positive slope, while curve 211 has a negative slope in this period. From trace 212, it can be seen that the negative DC magnetization steadily decreases due to the low demagnetization in the freewheeling intervals.

The magnetization speed is proportional to the applied voltage. If it is a factor K in the propellant phase, it is the factor K * UVf / Uzk in the freewheeling phase. Likewise, the integration rate has to behave corresponding to the currents [00222] Iint = (U55-Uf) / RintGl * 24, and

Eq. 25 [00223] Iint (U55-Uf) / Rent [00224] are proportional. It applies: 22/39

Austrian Patent Office AT505 507B1 2010-03-15

Eq. 26

Eq. 27 [00225] Uzk / Uvf Iint / Ient [00226] and with Eq. 24, 25 therefore:

[00227] ReNT = RI94 = R | NT * U2k / UvF

If the maximum pulse width of 100% of a pulse to the next permanently reduced to 0%, so the transformer magnetization degrades due to the demagnetization against the Ventilflußspannungen in time TE = T * Uzk / (4 * UVf) from. In the numerical example, TE is 20 periods of the switching frequency of the inverter.

If, for example, UZK 400 volts and UVF 5 volts, so results with the previously calculated resistor 58 R! Nt resistor 194 RENT to REnt = 528kQ.

Furthermore, the integrator in FIG. 14 is connected to the damping resistor 198, which is connected in parallel to the capacitor 59 to the lines 60, 62. With damping resistor 198, the attenuation of the distance TH = LH / Ri = Rd * Cint is taken into account. Resistor 198 is calculated to be [00231] Rd = Lh / (R * Cint). Eq. 28 [00232] Resistor R, is the sum of the resistors located in the respective current paths and should be approximately equal in symmetrical structure in all cases. For the values [00233] LH = 1 mH, R, = 100mQ, C | NT = 1 nF, the resistance 198 RD is RD = 10 Ω.

The values for REnt and RD from the numerical example show that here the linear demagnetization against the valve flux voltages in the freewheeling phases outweighs the demagnetization due to the weak damping by an order of magnitude.

REFERENCE IDENTIFICATION 1 supply line 2 supply line 3 line 4 line 5 line 6 line 7 drive circuit 8 switch 9 diode 10 drive circuit 11 switch 12 diode 13 inverter 14 switch 15 diode 16 drive circuit 17 switch 18 diode 19 drive circuit 20 switch 21 diode 22 drive circuit 23 switch 24 diode 25 Drive circuit 26 Inverter 27 Capacitor 28 Capacitor 23/39 Austrian Patent Office 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 AT505 507 B1 2010-03-15 T ransformator primary voltage

Transformer supplying network

Input rectifier

Output rectifier

load

Supply voltage, DC voltage, DC link voltage

management

management

management

management

contraption

regulator

management

Pulse width modulator, modulator

Link capacitor

management

management

management

management

DC converter

contraption

inverter

inverter

Zener diode

resistance

management

management

management

resistance

capacitor

management

operational amplifiers

management

comparator

comparator

flop

flop

inverter

Inverter AND gates AND gates

operational amplifiers

tension

integrator circuit

Electronics supply voltage

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management

electronic ground

logic circuit

logic circuit

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Prefilter 24/39 AT505 507 B1 2010-03-15 Austrian

Patent Office 84-92 93,94 95 96 97 98 99 100 101-104 105 106-115 116 117 118 119 120 121 122,123 124-131 132 133 134 135-144 145 146 147 148 149 150 151 152 153 154-157 158 159 160 161 162,163 164-166 167 168 169 170 171 172-175 176 177 178 179 180 181 182 183,184 185,186 187,188 Diagrams Ramp signals Setpoint signal Operating status Operating state Transformer magnetization, magnetization signal Pulse duration Pulse duration Time points Amplitude Time points Amplitude Value Point of time Amplitude Time Value Time points Diagrams Ramp signal Operating state Operating state Time points Line OR gate AND gate Inverter Line Magnetization curve Magnetization curve Value Value Points Value Magnetization curve Resistance Line Diode Ope ratio nsve rstrength r Resistance Operational amplifier Resistance Line Operational amplifier Resistors Line Control circuit Switch Control circuit Switch XOR gate Line AND gate Lines Switch 25/39

Claims (21)

AT505 507B1 2010-03-15 Austrian Patent Office 189,190 Control circuits 191,192 AND gate 193 Line 194 Resistor 195,196 lines 197 Induction limiting circuit 198 Resistance 199 Voltage 200-210 Diagrams 211,212 Magnetization curves 219,220 Points in time 221 Resistor 222 Zener diode Claims 1. Method for controlling alternating to a DC voltage switched transformers, in particular of pulse width modulated half and full bridge converters or phase shift controlled full bridge converters or inverters, wherein either a primary coil of the transformer or the DC supply voltage is alternately reversed and a period of time over which the primary coil is connected positively or negatively to the DC circuit of a required height of an output of a connected to a secondary winding of the transformer, preferably connected via a rectifier consumer characterized in that a device 40 or 50 receives or generates a signal corresponding to the primary voltage at the transformer, subsequently generating therefrom a magnetization signal corresponding to the magnetization of the transformer which continuously compares the magnetization signal with a positive and a negative critical value, which are fixed in device 40 or 50, and device 40 or 50 shortens a time duration of a positive or negative pulse generated at the required change of the output at the primary winding of the transformer when the magnetization signal has reached the positive or negative critical value. 2. The method according to claim 1, characterized in that the magnetization signal generates an integrator which integrates the signal corresponding to the transformer primary voltage. 3. The method according to claim 1 or 2, characterized in that the transformer primary voltage is fed back to the device 40. 4. The method according to one or more of claims 1 to 3, characterized in that an increase in the supplying DC voltage leads to a reduction in absolute value of the positive and the negative critical value in device 40. 5. The method according to one or more of claims 1 to 4, characterized in that an increase in the supplying DC voltage in device 40 causes an increase in the integration speed. 6. The method according to claim 1 or 2, characterized in that device 50 controls the integrator with its output signals. 7. The method according to claim 6, characterized in that the magnetization signal, when the pulse width is withdrawn at the transformer decreases in magnitude. 8. The method according to claim 7, characterized in that the magnetization signal decreases linearly in the freewheeling intervals. 9. The method according to claim 7, characterized in that the magnetization signal is weakly attenuated during demagnetization, or during the entire period of the switching frequency of the inverter. (Fig. 14) 26/39 Austrian Patent Office AT505 507B1 2010-03-15 Device 40 for carrying out the method according to one or more of claims 1 to 3, characterized in that the input of an integrator 73 from the output of a voltage detection device, e.g. a magnetic voltage converter 49, which is connected in parallel on the input side of the primary winding of transformer 30, is supplied with a signal 72 corresponding to the transformer primary voltage 29, the output of the integrator 73 is fed to the input of a comparator 63, at its second input a positive critical Value 55, the output of integrator 73 is connected to the input of another comparator 64, to whose second input a negative critical value 56 is set, the outputs of the comparators 63, 64 each to an input of a logic circuit 78 or 79 The logic circuit 78 or 79 on further inputs receives the durations of the pulses 45, 46 generated in response to a required change in the output quantity, and device 40 with its outputs 5, 6 of the logic circuit 78 or 79 obtains the periods 99,100 of positive and negative voltage pulses on the transformer sets. (Figs 6,7) 11. Device 40 for carrying out the method according to one or more of claims 1 to 5 and claim 10, characterized in that an input resistor 58 of the integrator 73 is selected so that the magnetizing signal occurring at the integrator output 62 upon application of the maximum operating voltage to the primary winding of transformer 30 within half a period of the switching frequency of the inverter of the negative 56 to the positive critical value 55 increases. 12. Device 40 according to claim 11, characterized in that integrator 73 is added a further input resistor 175 to an input 176 to which a signal from an amplifier 171 is applied, which also follows the course of a fed-back transformer voltage 72 and its amplitude of the fleas the DC supply voltage minus its lower limit, the fleas of the minimum operating voltage, is proportional. (Fig. 9) Device 40 according to claim 12, characterized in that the magnitudes of the critical values 55, 56 are equal to the amplitude of voltage 72 at minimum operating voltage minus the forward voltage of a clamping diode 162 or 163. 14. Device 40 according to claim 12 or 13, characterized in that the diodes 162,163, the amplitude of the signal, the voltage 72 follows, at the input 161 of a buffer amplifier 168 limit to that amount corresponding to the minimum operating voltage, an operational amplifier 164 voltage 72 inverted and operational amplifier 171 invert and add the output signals of the operational amplifiers 164, 168 so that the amplitude of the signal at its output 176 is proportional to the DC supply voltage minus its lower limit. 15. Device 40 according to one or more of claims 12 to 14, characterized in that resistor 175 is dimensioned according to equation 22. 16. Device 50 for carrying out the method according to claim 1 or 2, characterized in that the output at the outputs 5, 6 of the logic circuit 78 or 79 period for the positive and the negative pulse to transformer 30 and integrator 73 controls. (Fig. 13) 17. The device 50 according to claim 16, characterized in that the input resistor 58 of integrator 73 is selected so that the magnetizing signal occurring at the integrator output 62 when applying a constant voltage, advantageously the positive critical voltage 55 to resistor 58 within half a period of the switching frequency of the inverter increases from the negative 56 to the positive critical value 55. 18. Apparatus 50 for carrying out the method according to one or more of claims 8, 16 or 17, characterized in that integrator 73 has an additional input 193 with input resistance 194 added, whose duration of intervention from the outputs 5, 27/39 Austrian Patent Office AT505 507B1 The logic circuit 78 or 79 is determined and the direction of its engagement is controlled by the output signal of a comparator 213 whose output 216 indicates whether the magnetization signal is positive or negative. (Figs. 19. Device 50 according to claim 18, characterized in that input resistance 194 is dimensioned according to equation 27. 20. The device 50 according to claim 18 or 19, characterized in that the logic circuit 79 is used and the engagement time of the integrator input 193 is determined by an XOR operation of the signals on the control lines 5.6. 21. Device 50 for carrying out the method according to claim 9 and one or more of claims 16 to 20, characterized in that an integration capacitor 59, a damping resistor 198 is connected in parallel. For this 11 sheets drawings 28/39