AR102802A1 - Proporcionar instrucción de memoria de sistemas de memoria de acceso aleatorio dinámica (dram) mediante la utilización de bucles puerto a puerto, y métodos, sistemas y aparatos relacionados - Google Patents
Proporcionar instrucción de memoria de sistemas de memoria de acceso aleatorio dinámica (dram) mediante la utilización de bucles puerto a puerto, y métodos, sistemas y aparatos relacionadosInfo
- Publication number
- AR102802A1 AR102802A1 ARP150100027A ARP150100027A AR102802A1 AR 102802 A1 AR102802 A1 AR 102802A1 AR P150100027 A ARP150100027 A AR P150100027A AR P150100027 A ARP150100027 A AR P150100027A AR 102802 A1 AR102802 A1 AR 102802A1
- Authority
- AR
- Argentina
- Prior art keywords
- port
- systems
- puerto
- dram
- instruction
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
Landscapes
- Memory System (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Proporción de instrucción de memoria de sistemas de memoria de acceso aleatorio dinámica (DRAM) mediante la utilización de bucles puerto a puerto, y métodos, sistemas y aparatos relacionados. En un aspecto, un primer puerto dentro de un sistema DRAM se acopla a un segundo puerto por medio de una conexión de bucle. Una señal de instrucción se envía al primer puerto desde un System-on-Chip (SoC), y se pasa al segundo puerto a través de una conexión de bucle. La señal de instrucción luego se regresa al SoC, donde puede examinarse mediante un motor de instrucción de circuito cerrado del SoC. Un resultado de la instrucción correspondiente a un parámetro del hardware puede registrarse, y el proceso puede repetirse hasta que se logra un resultado óptimo para el parámetro del hardware en el motor de instrucción de circuito cerrado. Mediante el uso de una configuración de bucle puerto a puerto, los parámetros del sistema DRAM con respecto a la sincronización, la energía, y otros parámetros asociados con el sistema DRAM pueden instruirse más rápidamente y con un uso más bajo de la memoria de arranque.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461930980P | 2014-01-24 | 2014-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AR102802A1 true AR102802A1 (es) | 2017-03-29 |
Family
ID=53679614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ARP150100027A AR102802A1 (es) | 2014-01-24 | 2015-01-07 | Proporcionar instrucción de memoria de sistemas de memoria de acceso aleatorio dinámica (dram) mediante la utilización de bucles puerto a puerto, y métodos, sistemas y aparatos relacionados |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US9767868B2 (es) |
| EP (2) | EP3514796B1 (es) |
| JP (1) | JP6517221B2 (es) |
| KR (2) | KR20160113150A (es) |
| CN (2) | CN109872762B (es) |
| AR (1) | AR102802A1 (es) |
| TW (1) | TWI719933B (es) |
| WO (1) | WO2015112326A1 (es) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9767868B2 (en) | 2014-01-24 | 2017-09-19 | Qualcomm Incorporated | Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses |
| KR20180046428A (ko) | 2016-10-27 | 2018-05-09 | 삼성전자주식회사 | 메모리 장치 및 그것의 트레이닝 방법 |
| CN107861900B (zh) * | 2017-10-24 | 2019-12-31 | 华大半导体有限公司 | 信号选择模块和信号选择系统 |
| KR20190096753A (ko) | 2018-02-09 | 2019-08-20 | 삼성전자주식회사 | 클럭 트레이닝을 수행하는 시스템 온 칩 및 이를 포함하는 컴퓨팅 시스템 |
| EP3891909B1 (en) | 2019-02-19 | 2024-10-09 | Siemens Industry Software Inc. | Radio equipment test device |
| CN110941395B (zh) * | 2019-11-15 | 2023-06-16 | 深圳宏芯宇电子股份有限公司 | 动态随机存取存储器、内存管理方法、系统及存储介质 |
| KR20210136203A (ko) | 2020-05-06 | 2021-11-17 | 삼성전자주식회사 | 저장 장치 및 그것의 리트레이닝 방법 |
| CN116795430A (zh) * | 2023-06-27 | 2023-09-22 | 上海奎芯集成电路设计有限公司 | 存储器训练装置及存储器训练方法 |
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-
2015
- 2015-01-05 US US14/589,145 patent/US9767868B2/en active Active
- 2015-01-06 KR KR1020167021605A patent/KR20160113150A/ko not_active Application Discontinuation
- 2015-01-06 WO PCT/US2015/010218 patent/WO2015112326A1/en active Application Filing
- 2015-01-06 EP EP19160881.9A patent/EP3514796B1/en active Active
- 2015-01-06 EP EP15700821.0A patent/EP3097565A1/en not_active Withdrawn
- 2015-01-06 CN CN201910277089.9A patent/CN109872762B/zh active Active
- 2015-01-06 KR KR1020217014511A patent/KR102354764B1/ko active IP Right Grant
- 2015-01-06 JP JP2016547060A patent/JP6517221B2/ja active Active
- 2015-01-06 CN CN201580005381.5A patent/CN105934796B/zh active Active
- 2015-01-07 TW TW104100416A patent/TWI719933B/zh active
- 2015-01-07 AR ARP150100027A patent/AR102802A1/es unknown
-
2017
- 2017-06-14 US US15/622,772 patent/US9947377B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20150213849A1 (en) | 2015-07-30 |
| US9947377B2 (en) | 2018-04-17 |
| JP2017504905A (ja) | 2017-02-09 |
| CN109872762A (zh) | 2019-06-11 |
| KR20160113150A (ko) | 2016-09-28 |
| US20170278554A1 (en) | 2017-09-28 |
| EP3514796A3 (en) | 2019-12-04 |
| US9767868B2 (en) | 2017-09-19 |
| KR20210059017A (ko) | 2021-05-24 |
| TWI719933B (zh) | 2021-03-01 |
| EP3097565A1 (en) | 2016-11-30 |
| CN105934796A (zh) | 2016-09-07 |
| KR102354764B1 (ko) | 2022-01-21 |
| JP6517221B2 (ja) | 2019-05-22 |
| TW201539441A (zh) | 2015-10-16 |
| EP3514796B1 (en) | 2021-04-21 |
| WO2015112326A1 (en) | 2015-07-30 |
| EP3514796A2 (en) | 2019-07-24 |
| CN109872762B (zh) | 2022-11-29 |
| CN105934796B (zh) | 2019-04-19 |
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