AR099040A1 - Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram) - Google Patents
Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram)Info
- Publication number
- AR099040A1 AR099040A1 ARP150100030A ARP150100030A AR099040A1 AR 099040 A1 AR099040 A1 AR 099040A1 AR P150100030 A ARP150100030 A AR P150100030A AR P150100030 A ARP150100030 A AR P150100030A AR 099040 A1 AR099040 A1 AR 099040A1
- Authority
- AR
- Argentina
- Prior art keywords
- dram
- systems
- methods
- dynamic
- return channel
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Transceivers (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461925299P | 2014-01-09 | 2014-01-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AR099040A1 true AR099040A1 (es) | 2016-06-22 |
Family
ID=53495711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ARP150100030A AR099040A1 (es) | 2014-01-09 | 2015-01-07 | Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram) |
Country Status (10)
| Country | Link |
|---|---|
| US (2) | US9881656B2 (https=) |
| EP (1) | EP3092568A1 (https=) |
| JP (1) | JP2017503303A (https=) |
| KR (1) | KR20160106096A (https=) |
| CN (1) | CN105917312B (https=) |
| AR (1) | AR099040A1 (https=) |
| BR (1) | BR112016015961A2 (https=) |
| CA (1) | CA2932653A1 (https=) |
| TW (1) | TW201543498A (https=) |
| WO (1) | WO2015105948A1 (https=) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9881656B2 (en) | 2014-01-09 | 2018-01-30 | Qualcomm Incorporated | Dynamic random access memory (DRAM) backchannel communication systems and methods |
| US9728245B2 (en) | 2015-02-28 | 2017-08-08 | Intel Corporation | Precharging and refreshing banks in memory device with bank group architecture |
| US10783950B2 (en) * | 2015-09-02 | 2020-09-22 | Nvidia Corporation | Memory management systems and methods using a management communication bus |
| KR20190087893A (ko) | 2018-01-17 | 2019-07-25 | 삼성전자주식회사 | 클럭을 공유하는 반도체 패키지 및 전자 시스템 |
| US11036578B2 (en) | 2018-04-12 | 2021-06-15 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and memory systems including the same |
| CN110729006B (zh) * | 2018-07-16 | 2022-07-05 | 超威半导体(上海)有限公司 | 存储器控制器中的刷新方案 |
| US10747613B2 (en) * | 2018-09-07 | 2020-08-18 | Toshiba Memory Corporation | Pooled frontline ECC decoders in memory systems |
| CN114556431B (zh) * | 2019-10-29 | 2025-05-27 | Oppo广东移动通信有限公司 | 增强现实的3d重建 |
| US11392299B2 (en) | 2019-12-20 | 2022-07-19 | Micron Technology, Inc. | Multi-purpose signaling for a memory system |
| US11360695B2 (en) | 2020-09-16 | 2022-06-14 | Micron Technology, Inc. | Apparatus with combinational access mechanism and methods for operating the same |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57150227A (en) * | 1981-03-12 | 1982-09-17 | Nec Corp | Buffer circuit |
| CA2074307C (en) | 1991-07-29 | 1995-12-12 | Leslie J. Sell | Rope guide |
| JPH065069A (ja) * | 1992-06-18 | 1994-01-14 | Nec Corp | ダイナミック・ランダム・アクセス・メモリ |
| JP3376960B2 (ja) * | 1999-06-01 | 2003-02-17 | 日本電気株式会社 | 半導体記憶装置およびそれを用いたシステム |
| JP4069078B2 (ja) * | 2004-01-07 | 2008-03-26 | 松下電器産業株式会社 | Ｄｒａｍ制御装置およびｄｒａｍ制御方法 |
| US7627804B2 (en) | 2006-06-30 | 2009-12-01 | Intel Corporation | Memory device with speculative commands to memory core |
| US7937641B2 (en) | 2006-12-21 | 2011-05-03 | Smart Modular Technologies, Inc. | Memory modules with error detection and correction |
| KR101308047B1 (ko) | 2007-02-08 | 2013-09-12 | 삼성전자주식회사 | 메모리 시스템, 이 시스템을 위한 메모리, 및 이 메모리를위한 명령 디코딩 방법 |
| US8132074B2 (en) | 2007-11-19 | 2012-03-06 | Intel Corporation | Reliability, availability, and serviceability solutions for memory technology |
| US9158616B2 (en) | 2009-12-09 | 2015-10-13 | Intel Corporation | Method and system for error management in a memory device |
| US8392650B2 (en) * | 2010-04-01 | 2013-03-05 | Intel Corporation | Fast exit from self-refresh state of a memory device |
| US9432298B1 (en) * | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
| KR101873526B1 (ko) | 2011-06-09 | 2018-07-02 | 삼성전자주식회사 | 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법 |
| KR101253199B1 (ko) * | 2011-07-25 | 2013-04-10 | 엘지전자 주식회사 | 조명 장치 |
| KR101962874B1 (ko) * | 2012-04-24 | 2019-03-27 | 삼성전자주식회사 | 메모리 장치, 메모리 컨트롤러, 메모리 시스템 및 이의 동작 방법 |
| US9881656B2 (en) | 2014-01-09 | 2018-01-30 | Qualcomm Incorporated | Dynamic random access memory (DRAM) backchannel communication systems and methods |
-
2015
- 2015-01-07 US US14/591,056 patent/US9881656B2/en active Active
- 2015-01-07 AR ARP150100030A patent/AR099040A1/es unknown
- 2015-01-08 CN CN201580004085.3A patent/CN105917312B/zh active Active
- 2015-01-08 TW TW104100580A patent/TW201543498A/zh unknown
- 2015-01-08 BR BR112016015961A patent/BR112016015961A2/pt not_active IP Right Cessation
- 2015-01-08 EP EP15701617.1A patent/EP3092568A1/en not_active Withdrawn
- 2015-01-08 CA CA2932653A patent/CA2932653A1/en not_active Abandoned
- 2015-01-08 WO PCT/US2015/010583 patent/WO2015105948A1/en not_active Ceased
- 2015-01-08 JP JP2016544821A patent/JP2017503303A/ja active Pending
- 2015-01-08 KR KR1020167020653A patent/KR20160106096A/ko not_active Withdrawn
-
2017
- 2017-12-20 US US15/849,463 patent/US10224081B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CA2932653A1 (en) | 2015-07-16 |
| CN105917312B (zh) | 2019-03-08 |
| EP3092568A1 (en) | 2016-11-16 |
| US20180114553A1 (en) | 2018-04-26 |
| JP2017503303A (ja) | 2017-01-26 |
| US9881656B2 (en) | 2018-01-30 |
| TW201543498A (zh) | 2015-11-16 |
| BR112016015961A2 (pt) | 2017-08-08 |
| KR20160106096A (ko) | 2016-09-09 |
| US20150194197A1 (en) | 2015-07-09 |
| CN105917312A (zh) | 2016-08-31 |
| WO2015105948A1 (en) | 2015-07-16 |
| US10224081B2 (en) | 2019-03-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FB | Suspension of granting procedure |