AR034544A1 - Metodo para reducir la carga de interrupciones en el procesador - Google Patents

Metodo para reducir la carga de interrupciones en el procesador

Info

Publication number
AR034544A1
AR034544A1 ARP010100553A ARP010100553A AR034544A1 AR 034544 A1 AR034544 A1 AR 034544A1 AR P010100553 A ARP010100553 A AR P010100553A AR P010100553 A ARP010100553 A AR P010100553A AR 034544 A1 AR034544 A1 AR 034544A1
Authority
AR
Argentina
Prior art keywords
interruptions
load
shared memory
processor
operating system
Prior art date
Application number
ARP010100553A
Other languages
English (en)
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of AR034544A1 publication Critical patent/AR034544A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

Un método para reducir la carga de interrupciones en un sistema de múltiples procesadores, por el cual dos procesadores centrales que ejecutan un sistema operativo en tiempo real se pueden comunicar entre sí, usando una memoria compartida. Se implementan, preferentemente en lógica, un puntero Inicio y un puntero Fin. Mediante la detección de una diferencia en los valores lógicos de los dos punteros, la CPU receptora recibe las interrupciones sólo cuando han llegado a la memoria compartida nuevos datos de la CPU emisora, y la memoria compartida estaba vacía. Por consiguiente, el sistema operativo no se ve pertubado por interrupciones innecesarias y, de ese modo, la carga de interrupciones resulta baja.
ARP010100553A 2000-02-09 2001-02-07 Metodo para reducir la carga de interrupciones en el procesador AR034544A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/500,653 US6535942B1 (en) 2000-02-09 2000-02-09 Method for reducing processor interrupt load

Publications (1)

Publication Number Publication Date
AR034544A1 true AR034544A1 (es) 2004-03-03

Family

ID=23990360

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP010100553A AR034544A1 (es) 2000-02-09 2001-02-07 Metodo para reducir la carga de interrupciones en el procesador

Country Status (5)

Country Link
US (1) US6535942B1 (es)
AR (1) AR034544A1 (es)
AU (1) AU3254101A (es)
TW (1) TW511035B (es)
WO (1) WO2001059567A2 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6851000B2 (en) * 2000-10-03 2005-02-01 Broadcom Corporation Switch having flow control management
US7363412B1 (en) * 2004-03-01 2008-04-22 Cisco Technology, Inc. Interrupting a microprocessor after a data transmission is complete
US20050283550A1 (en) * 2004-06-18 2005-12-22 Honeywell International Inc. Method and architecture of a coupling system for microprocessors and logic devices
US7437546B2 (en) * 2005-08-03 2008-10-14 Intel Corporation Multiple, cooperating operating systems (OS) platform system and method
EP2063581A1 (en) * 2007-11-20 2009-05-27 STMicroelectronics (Grenoble) SAS Transferring a stream of data between first and second electronic devices via a network on-chip
DE102009047121A1 (de) 2009-11-25 2011-05-26 Robert Bosch Gmbh Verfahren zum Erzeugen von Sequenzen
WO2012014285A1 (ja) * 2010-07-27 2012-02-02 富士通株式会社 割込制御方法、マルチコアプロセッサシステム、および割込制御プログラム
US9880784B2 (en) * 2016-02-05 2018-01-30 Knuedge Incorporated Data routing and buffering in a processing system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179707A (en) 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
JP3335726B2 (ja) 1993-09-24 2002-10-21 株式会社エフ・エフ・シー マルチプロセッサシステムにおけるデータ保護装置
US5648777A (en) * 1993-12-16 1997-07-15 Lucent Technologies Inc. Data converter with FIFO
US6085277A (en) * 1997-10-15 2000-07-04 International Business Machines Corporation Interrupt and message batching apparatus and method
US6240483B1 (en) * 1997-11-14 2001-05-29 Agere Systems Guardian Corp. System for memory based interrupt queue in a memory of a multiprocessor system

Also Published As

Publication number Publication date
AU3254101A (en) 2001-08-20
US6535942B1 (en) 2003-03-18
TW511035B (en) 2002-11-21
WO2001059567A3 (en) 2002-01-17
WO2001059567A2 (en) 2001-08-16

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