BRPI0703672A - sistema e método para gerenciar interrupções de gerenciamento de sistema em um sistema de computador de multiprocessador - Google Patents

sistema e método para gerenciar interrupções de gerenciamento de sistema em um sistema de computador de multiprocessador

Info

Publication number
BRPI0703672A
BRPI0703672A BRPI0703672-8A BRPI0703672A BRPI0703672A BR PI0703672 A BRPI0703672 A BR PI0703672A BR PI0703672 A BRPI0703672 A BR PI0703672A BR PI0703672 A BRPI0703672 A BR PI0703672A
Authority
BR
Brazil
Prior art keywords
interrupt
managing
multiprocessor computer
outages
processors
Prior art date
Application number
BRPI0703672-8A
Other languages
English (en)
Inventor
Vijay Nijhawan
Madhusudhan Rangarajan
Bi-Chong Wang
Wuxian Wu
Original Assignee
Dell Products Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dell Products Lp filed Critical Dell Products Lp
Publication of BRPI0703672A publication Critical patent/BRPI0703672A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)

Abstract

SISTEMA E MéTODO PARA GERENCIAR INTERRUPçõES DE GERENCIAMENTO DE SISTEMA EM UM SISTEMA DE COMPUTADOR DE MULTIPROCESSADOR. São descritos sistema e método nos quais, durante a execução de uma seqüência de tratamento de interrupção em um dos processadores de um sistema multiprocessadores, um processador grava um código de motivo em um registro de estado para identificar a causa da interrupção. O código da 3105 do sistema grava em um registro de iniciação de interrupção para fazer com que cada um dos processadores entre em uma seqüência de tratamento de interrupção. Cada um dos processadores do sistema trata a interrupção com base no conteúdo do registro do estado, fazendo com que cada um dos processadores trate sincronizadamente uma interrupção para um evento que, de outra forma, resultaria em uma interrupção local.
BRPI0703672-8A 2006-09-29 2007-09-27 sistema e método para gerenciar interrupções de gerenciamento de sistema em um sistema de computador de multiprocessador BRPI0703672A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/540,804 US20080082710A1 (en) 2006-09-29 2006-09-29 System and method for managing system management interrupts in a multiprocessor computer system

Publications (1)

Publication Number Publication Date
BRPI0703672A true BRPI0703672A (pt) 2008-06-03

Family

ID=38701890

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0703672-8A BRPI0703672A (pt) 2006-09-29 2007-09-27 sistema e método para gerenciar interrupções de gerenciamento de sistema em um sistema de computador de multiprocessador

Country Status (9)

Country Link
US (1) US20080082710A1 (pt)
CN (1) CN101154202B (pt)
BR (1) BRPI0703672A (pt)
DE (1) DE102007046947B4 (pt)
FR (1) FR2907932A1 (pt)
GB (1) GB2442354B (pt)
IE (1) IE20070692A1 (pt)
SG (1) SG141399A1 (pt)
TW (1) TWI401604B (pt)

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US7802042B2 (en) * 2007-12-28 2010-09-21 Intel Corporation Method and system for handling a management interrupt event in a multi-processor computing device
US20090172232A1 (en) * 2007-12-28 2009-07-02 Zimmer Vincent J Method and system for handling a management interrupt event
US7707344B2 (en) * 2008-01-29 2010-04-27 International Business Machines Corporation Interrupt mitigation on multiple network adapters
CN101308469B (zh) * 2008-07-07 2011-08-10 成都市华为赛门铁克科技有限公司 一种软中断负载均衡的实现方法及设备
US7779191B2 (en) * 2008-07-29 2010-08-17 Nvidia Corporation Platform-based idle-time processing
US8122176B2 (en) * 2009-01-29 2012-02-21 Dell Products L.P. System and method for logging system management interrupts
KR20110097447A (ko) * 2010-02-25 2011-08-31 삼성전자주식회사 인터럽트 프록시 기능을 구비한 시스템 온 칩 및 그에 따른 인터럽트 프록시 처리방법
GB2484729A (en) 2010-10-22 2012-04-25 Advanced Risc Mach Ltd Exception control in a multiprocessor system
CN102591821B (zh) * 2011-01-12 2015-08-26 中兴通讯股份有限公司 处理数据上报中断控制方法及装置
CN108399135B (zh) * 2018-03-02 2021-05-18 郑州云海信息技术有限公司 一种磁盘设备识别的控制方法以及相关装置

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US4495569A (en) * 1982-06-28 1985-01-22 Mitsubishi Denki Kabushiki Kaisha Interrupt control for multiprocessor system with storage data controlling processor interrupted by devices
KR940001878B1 (ko) * 1990-03-08 1994-03-10 가부시끼가이샤 히다찌세이사꾸쇼 멀티 프로세서시스템 및 인터럽션 제어장치
US5125093A (en) * 1990-08-14 1992-06-23 Nexgen Microsystems Interrupt control for multiprocessor computer system
JP2729343B2 (ja) * 1992-08-28 1998-03-18 三菱電機株式会社 複数個の処理装置を有する情報処理システムおよびこの情報処理システムにおいて用いられる制御装置ならびに処理装置
US5671424A (en) * 1994-02-02 1997-09-23 Advanced Micro Devices, Inc. Immediate system management interrupt source with associated reason register
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US5708813A (en) * 1994-12-12 1998-01-13 Digital Equipment Corporation Programmable interrupt signal router
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US6272618B1 (en) * 1999-03-25 2001-08-07 Dell Usa, L.P. System and method for handling interrupts in a multi-processor computer
US6282601B1 (en) * 1999-03-31 2001-08-28 International Business Machines Corporation Multiprocessor data processing system and method of interrupt handling that facilitate identification of a processor requesting a system management interrupt
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TW498213B (en) * 2001-04-18 2002-08-11 Via Tech Inc Method and chipset for supporting interrupts of system management mode in multiple-CPU system
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US7689747B2 (en) * 2005-03-28 2010-03-30 Microsoft Corporation Systems and methods for an augmented interrupt controller and synthetic interrupt sources

Also Published As

Publication number Publication date
GB2442354A (en) 2008-04-02
SG141399A1 (en) 2008-04-28
FR2907932A1 (fr) 2008-05-02
IE20070692A1 (en) 2008-05-14
DE102007046947A1 (de) 2008-05-21
TW200825925A (en) 2008-06-16
CN101154202A (zh) 2008-04-02
DE102007046947B4 (de) 2017-10-12
GB2442354B (en) 2009-06-17
CN101154202B (zh) 2012-01-25
US20080082710A1 (en) 2008-04-03
TWI401604B (zh) 2013-07-11
GB0719035D0 (en) 2007-11-07

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

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