AR019445A1 - Metodo y aparato para determinar una metrica en un algoritmo de decodificacion que usa un modulo de procesamiento de n bits - Google Patents
Metodo y aparato para determinar una metrica en un algoritmo de decodificacion que usa un modulo de procesamiento de n bitsInfo
- Publication number
- AR019445A1 AR019445A1 ARP990103588A ARP990103588A AR019445A1 AR 019445 A1 AR019445 A1 AR 019445A1 AR P990103588 A ARP990103588 A AR P990103588A AR P990103588 A ARP990103588 A AR P990103588A AR 019445 A1 AR019445 A1 AR 019445A1
- Authority
- AR
- Argentina
- Prior art keywords
- bit
- flexible
- words
- processing module
- word
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 239000002131 composite material Substances 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3988—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Se usa método y aparato para determinar una métrica de un algoritmo de decodificacion, tal como un algoritmo de Viterbi, usando un modulo de procesamientode n bits sobre la base de multiples palabras de entrada flexible de m bits donde n3 2xm. Latéc nica comprende: recibir multiples palabras de entrada flexiblede m bits; ensamblar por lo menos dos de las multiples palabras de entrada flexible de m bits en una sola palabra de entrada flexible compuesta de n bits;calcular las respectivasdistancia s entre las por lo menos dos palabras de entrada flexible de la palabra de entrada flexible compuesta y los valores depalabra de codigo esperados para introducir una palabra de distancia compuesta; sumar las respectivas distancias paraproducir la mé trica; y extraer lamétrica. El modulo de procesamiento de n bits puede comprender un modulo de procesamiento de 16 bits que emplea palabras de 16 bits y las palabras de entradaflexible de m bits pueden comprender, cada una, unapalabra de 4 bits. El procesamiento de las multiples palabras de entrada flexible en bloque aumenta lavelocidad y la velocidad de transferencia de informacion del decodificador y reduce los requisitos de memoria del mismo.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/120,203 US6334202B1 (en) | 1998-07-22 | 1998-07-22 | Fast metric calculation for Viterbi decoder implementation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AR019445A1 true AR019445A1 (es) | 2002-02-20 |
Family
ID=22388862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ARP990103588A AR019445A1 (es) | 1998-07-22 | 1999-07-21 | Metodo y aparato para determinar una metrica en un algoritmo de decodificacion que usa un modulo de procesamiento de n bits |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US6334202B1 (es) |
| EP (1) | EP1099312B1 (es) |
| JP (1) | JP4149674B2 (es) |
| KR (1) | KR100673713B1 (es) |
| CN (1) | CN1139190C (es) |
| AR (1) | AR019445A1 (es) |
| AT (1) | ATE218016T1 (es) |
| AU (1) | AU758068B2 (es) |
| CA (1) | CA2337190C (es) |
| DE (1) | DE69901566T2 (es) |
| TW (1) | TW423226B (es) |
| WO (1) | WO2000005819A1 (es) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1220455A1 (en) * | 2000-12-29 | 2002-07-03 | Motorola, Inc. | Viterbi decoder, method and unit therefor |
| US6823027B2 (en) * | 2001-03-05 | 2004-11-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for enhancing soft-value information |
| US6931612B1 (en) * | 2002-05-15 | 2005-08-16 | Lsi Logic Corporation | Design and optimization methods for integrated circuits |
| US8290095B2 (en) * | 2006-03-23 | 2012-10-16 | Qualcomm Incorporated | Viterbi pack instruction |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537444A (en) * | 1993-01-14 | 1996-07-16 | At&T Corp. | Extended list output and soft symbol output viterbi algorithms |
| US5835960A (en) * | 1994-01-07 | 1998-11-10 | Cirrus Logic, Inc. | Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus |
| EP0679000A1 (en) * | 1994-04-22 | 1995-10-25 | Koninklijke Philips Electronics N.V. | Soft quantisation |
| US5687188A (en) * | 1994-10-11 | 1997-11-11 | Motorola, Inc. | Method of producing an adjusted metric |
| KR0138875B1 (ko) | 1994-12-23 | 1998-06-15 | 양승택 | 비터비 복호기의 가지 메트릭 모듈 |
| US5907842A (en) * | 1995-12-20 | 1999-05-25 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |
| US5862190A (en) * | 1995-12-29 | 1999-01-19 | Motorola, Inc. | Method and apparatus for decoding an encoded signal |
| US5881075A (en) | 1996-03-18 | 1999-03-09 | Samsung Electronics Co., Ltd. | Viterbi decoder |
| US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
| US5973628A (en) * | 1997-10-03 | 1999-10-26 | Cisco Technology, Inc. | Parallel variable bit encoder |
| US6065093A (en) * | 1998-05-15 | 2000-05-16 | International Business Machines Corporation | High bandwidth narrow I/O memory device with command stacking |
-
1998
- 1998-07-22 US US09/120,203 patent/US6334202B1/en not_active Expired - Lifetime
-
1999
- 1999-07-15 CA CA002337190A patent/CA2337190C/en not_active Expired - Fee Related
- 1999-07-15 CN CNB998089400A patent/CN1139190C/zh not_active Expired - Fee Related
- 1999-07-15 KR KR1020017000294A patent/KR100673713B1/ko not_active IP Right Cessation
- 1999-07-15 JP JP2000561709A patent/JP4149674B2/ja not_active Expired - Fee Related
- 1999-07-15 AU AU52827/99A patent/AU758068B2/en not_active Ceased
- 1999-07-15 WO PCT/EP1999/005014 patent/WO2000005819A1/en active IP Right Grant
- 1999-07-15 AT AT99938255T patent/ATE218016T1/de not_active IP Right Cessation
- 1999-07-15 DE DE69901566T patent/DE69901566T2/de not_active Expired - Lifetime
- 1999-07-15 EP EP99938255A patent/EP1099312B1/en not_active Expired - Lifetime
- 1999-07-19 TW TW088112191A patent/TW423226B/zh not_active IP Right Cessation
- 1999-07-21 AR ARP990103588A patent/AR019445A1/es not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| EP1099312B1 (en) | 2002-05-22 |
| DE69901566D1 (de) | 2002-06-27 |
| JP2002521907A (ja) | 2002-07-16 |
| US6334202B1 (en) | 2001-12-25 |
| TW423226B (en) | 2001-02-21 |
| KR100673713B1 (ko) | 2007-01-23 |
| CN1310884A (zh) | 2001-08-29 |
| EP1099312A1 (en) | 2001-05-16 |
| CN1139190C (zh) | 2004-02-18 |
| AU758068B2 (en) | 2003-03-13 |
| DE69901566T2 (de) | 2003-01-16 |
| CA2337190C (en) | 2007-04-03 |
| JP4149674B2 (ja) | 2008-09-10 |
| ATE218016T1 (de) | 2002-06-15 |
| CA2337190A1 (en) | 2000-02-03 |
| AU5282799A (en) | 2000-02-14 |
| KR20010071792A (ko) | 2001-07-31 |
| WO2000005819A1 (en) | 2000-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6844833B2 (en) | Methods and apparatus for constant-weight encoding and decoding | |
| BR9714208A (pt) | Método e equipamento para transmitir e receber dados de código concatenados | |
| BR9909975A (pt) | Processo de transmitir informação, sistema de transmissão de diversidade para transmitir informação, processo de receber informação, e, terminal de usuário para receber informação | |
| NO20053044L (no) | Koding av multiple meldinger i audiodata og dekoding av samme. | |
| TW200614683A (en) | Cyclic redundancy check generation circuit | |
| MY119831A (en) | Viterbi decoding apparatus and viterbi decoding method | |
| DE60313832D1 (de) | Verfahren und System für die Generierung von Low Density Parity Check (LDPC) Codes | |
| BR9907819A (pt) | Codificador/decodificador com estrutura concatenada em série em sistema de comunicação | |
| KR960043552A (ko) | 에러정정 부호화 복호화방법 및 이 방법을 사용하는 회로 | |
| AR020262A1 (es) | Un metodo para desarrollar un circuito generador para generar, paralelamente, un codigo para la verificacion ciclica de redundancia y un circuito generadorpara generar, paralelamente, dicho codigo para la verificacion ciclica de redundancia | |
| BR0302820A (pt) | Troca de mensagens de blocos componentes intradecodificador | |
| DE3371008D1 (en) | Multiprocessor computer system comprising n parallel operating computer modules, and computer module for use in such a multiprocessor computer system | |
| AR017944A1 (es) | Dispositivo para codificar/decodificar un flujo de bit de datos, el portador de grabacion obtenido y el metodo de codificar con el dispositivo paracodificar | |
| AR019445A1 (es) | Metodo y aparato para determinar una metrica en un algoritmo de decodificacion que usa un modulo de procesamiento de n bits | |
| DE602004011828D1 (en) | Empfänger-corporation | |
| ES462082A1 (es) | Procedimiento y elaborador para generar palabras de m + n bits para sistemas controlados de programas memorizados. | |
| FI851264L (fi) | System foer korrigering av fel i digitala signaler i reed-solomon-kod. | |
| JP2011101334A (ja) | 擬似直交符号発生器 | |
| AR033487A1 (es) | Dispositivo para codificar/decodificar palabras de fuente de n-bit en palabras de canal de n-bit correspondientes y viceversa | |
| ATE219306T1 (de) | Turbo-code dekodierer | |
| AU2002222493A8 (en) | Decoder, system and method for decoding turbo block codes | |
| JPS5778608A (en) | Decoding method of reed-solomon code | |
| AR025875A1 (es) | Intercalador y metodo para intercalar una secuencia de bits de datos | |
| EP0835012A3 (en) | A DQPSK mapping circuit | |
| RU29816U1 (ru) | Кодирующее устройство помехоустойчивого кода |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FA | Abandonment or withdrawal |