JPH11112832A - Synchronizing separator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To separate synchronizing signals without causing synchronizing disturbance even to the input of video signals to which copy guard signals Scg are superimposed. SOLUTION: This circuit is provided with a clamp circuit 14, a sample-and- hold circuit 24, a voltage divider circuit 18 and a slice circuit 20. In a fly-back period in which the copy guard signals are superimposed, between sampling voltage Vd and Vu sampled and held by the sample-and-hold circuit 24, Vu is made higher than a threshold value Vt and lower than a set value Es. Since the set value Es is set to a value lower than the peak level Vp of the copy guard signals, the sampling voltage Vu does not become Vp. Thus, a slice level SL (=(Vd+Vu) /2) prepared in the voltage divider circuit 18 becomes a voltage lower than a black level Vb and stable synchronizing separation is performed without causing the synchronizing disturbance even to the input of the video signals to which the copy guard signals are superimposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog composite video signal (also referred to as a composite video signal) such as a TV signal (video signal from a television broadcasting station) or a VTR signal (video signal from a video tape recorder). The present invention relates to a sync separation circuit (for example, a sync separation IC) for separating a sync signal (composite sync signal or vertical sync signal) from the sync signal.

[0002]

2. Description of the Related Art Conventionally, this kind of sync separation IC 10 is shown in FIG.
It was configured as shown. That is, the lower end level of the composite video signal input via the coupling capacitor 12 is adjusted to a predetermined clamp voltage Vc (constant DC voltage) by the clamp circuit 14 and is input to the sample and hold circuit 16. This sample and hold circuit 16
The voltage immediately after the falling of the clamped composite video signal is sampled and compared with a threshold value Vt (threshold voltage).
(Corresponding to a sync chip), and after holding the sampling voltage Vd, sample the voltage immediately after the rising edge of the clamped composite video signal, and calculate the sampling voltage Vu when the sampling value is equal to or higher than the threshold value Vt. Hold.

[0003] The voltage dividing circuit 18 comprises a sample and hold circuit 1.
A slice level SL (SL = ((Vd + Vu) / 2)) is created based on the sampling voltages Vd and Vu held in step 6, and a slice circuit (also referred to as a slicer, hereinafter the same)
Reference numeral 20 extracts a level portion equal to or lower than the slice level SL from the composite video signal clamped by the clamp circuit 14 and uses it as a synchronization signal. Specifically, the clamp circuit 1
Assuming that the synchronizing signal superimposed on the retrace period of the composite video signal clamped at 4 is a signal as shown in FIG. 6A, the synchronizing signal extracted by the slice circuit 20 is as shown in FIG. become. In FIG. 6A, Vb represents a black level set slightly higher than the pedestal level (blank elimination level, black level), SL represents a slice level, and SL-Vc is represented by the following equation (1). be able to. SL−Vc = １ ／ (Vu−Vd) = １ ／ (Vb−Vc) (1)

[0004]

However, in the sync separation IC 10 shown in FIG. 5, as shown in FIG. 7, it is necessary to make copying impossible during a blanking period (for example, a back porch) of a composite video signal. When the copy guard signal Scg is superimposed, there is a problem that normal synchronization separation cannot be performed and synchronization is disturbed. That is,
In the flyback period P1 in which the horizontal synchronizing signal Sd is superimposed, the sampling voltages Vd and Vu held by the sample and hold circuit 16 are the clamp voltage Vc and the black level Vb, respectively. The level SL1 is lower than the black level Vb (Vb + Vc) /
2, there is no problem, but in the retrace period P2 in which the copy guard signal Scg is superimposed, the sample hold circuit 16
Of the sampling voltages Vd and Vu held by the above become the clamp voltage Vc and the peak level Vp (the peak level of the copy guard signal Scg), so that the slice level SL2 created by the voltage dividing circuit 18 is higher than the black level Vb (Vp + Vc). ) / 2, which makes it impossible to perform normal synchronization separation, causing a problem of synchronization disturbance. In FIG. 7, Sv represents a video signal, and black circles represent sampling points.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to perform stable synchronization separation without causing a synchronization disturbance even for an input of a composite video signal on which a copy guard signal Scg is superimposed. It is an object of the present invention to provide a sync separation circuit capable of performing the following.

[0006]

According to a first aspect of the present invention, there is provided a sync separation circuit comprising: a clamp circuit for adjusting a lower end level of a video signal on which a sync signal is superimposed to a clamp voltage Vc; and a video signal clamped by the clamp circuit. The voltage immediately after the falling is sampled, and the sampled value
t, the sampling voltage Vd is held, and after holding the sampling voltage Vd, the voltage immediately after the rising of the clamped video signal is sampled, and the sampled value is equal to or more than the threshold value Vt and the set value Es (Es is copy guard). (The set value for detecting the black level set to a value lower than the peak level of the signal)
u, and a slice level SL (SL = (Vd + Vu) /) based on the sampling voltages Vd and Vu held by the sample / hold circuit.
2) and a slice circuit for extracting a level portion below the slice level SL from the video signal clamped by the clamp circuit and using it as a synchronization signal.

In the blanking period in which the synchronizing signal of the video signal is superimposed, the sampling voltages Vd and Vu held by the sample and hold circuit are the clamp voltage Vc and the black level Vb, respectively. The slice level SL to be created is lower than the black level Vb (Vb + V
c) / 2. Copy guard signal S of video signal
In the flyback period in which cg is superimposed, the lower sampling voltage Vd held by the sample and hold circuit becomes the clamp voltage Vc, and the higher sampling voltage Vd
u is a voltage (normally, black level Vb) not less than the threshold value Vt and not more than the set value Es for detecting the black level. This set value E
Since s is set to a value lower than the peak level Vp of the copy guard signal, the higher sampling voltage Vu does not become the peak level Vp of the copy guard signal Scg. Therefore, the slice level SL created by the voltage divider circuit is lower than the black level Vb (for example, (Vb + V
c) / 2).

According to a second aspect of the present invention, in order to ensure that the slice level SL created by the voltage dividing circuit is lower than the black level Vb, the set value Es for black level detection is changed to the black level. Vb, which is higher than Vb and twice the black level Vb minus the clamp voltage Vc (2Vb−V
c) Lower voltage.

According to a third aspect of the present invention, there is provided a synchronization separating circuit, comprising: a clamp circuit; and a set value Esa (Esa is higher than the black level Vb and twice the black level Vb) of the video signal clamped by the clamp circuit. From the clamp voltage Vc
(A set value set to a voltage lower than 2Vb-Vc)), a peak clipper that cuts out and outputs a signal, and a voltage immediately after the falling of the output signal of the peak clipper is sampled. Is held when the sampling voltage Vd is equal to or lower than the threshold value Vt, the voltage immediately after the rising of the peak clipper output signal is sampled after holding the sampling voltage Vd, and the sampling is performed when the sampling value is equal to or higher than the threshold value Vt. A sample-and-hold circuit for holding a voltage Vu, and a sampling voltage Vd held by the sample-and-hold circuit,
Based on Vu, the slice level SL (SL = (Vd + V
u) / 2), and a slice circuit that extracts a level portion equal to or lower than the slice level SL from the video signal clamped by the clamp circuit and uses it as a synchronization signal. I do.

[0010] Of the video signal clamped by the clamp circuit, a signal equal to or greater than the set value Esa is truncated by the peak clipper and input to the sample-and-hold circuit, so that the copy guard signal Scg of the video signal is superimposed. In the line period, the higher sampling voltage Vu held by the sample and hold circuit is a voltage equal to or higher than the threshold value Vt and equal to or lower than the set value Esa. This set value Esa is (2V
Since the voltage is set to be lower than (b−Vc), the slice level SL created by the voltage divider becomes a voltage lower than the black level Vb (for example, (Vb + Vc) / 2).

According to a fourth aspect of the present invention, in the first, second or third aspect of the present invention, a sample-and-hold circuit is provided with a new sampling voltage so that a synchronization signal can be always taken out at a stable slice level SL. Vd and V
Until u is held, the holding of the sampling voltages Vd and Vu held immediately before is continued.

According to a fifth aspect of the present invention, a synchronization separating circuit detects a voltage Vd which is equal to or lower than a threshold value Vt among voltages immediately after falling of a video signal clamped by the clamp circuit. A voltage level detection circuit for detecting a voltage Vu that is equal to or higher than a threshold value Vt among the voltages immediately after the rising of the clamped video signal after the detection of the voltage Vd, and an average of the detection voltage Vu of the voltage level detection circuit during a certain period Tc Average value calculation circuit for calculating the value (Vu), and the average value (Vu) calculated by the average value calculation circuit
And a voltage dividing circuit for generating a slice level SL (SL = ((Vu) + Vd) / 2) based on the detection voltage Vd of the voltage level detection circuit, and a slice level SL or less of the video signal clamped by the clamp circuit And a slice circuit which takes out the level portion and uses it as a synchronization signal.

In a retrace period in which only the synchronization signal Sd of the video signal is superimposed, each of the voltages Vd and Vu detected by the voltage level detection circuit is the clamp voltage V
c, black level Vb. In the retrace period in which the copy guard signal Scg of the video signal is superimposed, the voltage Vd detected by the voltage level detection circuit is the clamp voltage V
The voltage Vu detected by the voltage level detection circuit becomes the black level Vb and the peak level Vp of the copy guard signal Scg. Therefore, by setting the fixed period Tc to an appropriate value (for example, one field period), the copy guard signal S is set within the fixed period Tc.
Since the number of pulses of cg can be reduced so as not to be a problem compared to the number of pulses of the synchronization signal Sd (for example, a horizontal synchronization signal), the voltage (Vu) averaged by the average value calculation circuit over the fixed period Tc is a copy guard. The value is close to the black level Vb, which is much lower than the peak level Vp of the signal Scg. Therefore, the slice level SL created by the voltage divider circuit is lower than the black level Vb (for example, (Vb + V
c) / 2).

According to a sixth aspect of the present invention, in order to obtain the averaged voltage (Vu) with high accuracy, the average value calculating circuit is replaced with a digital value Dvu by the detection voltage Vu of the voltage level detection circuit. An A / D conversion circuit for converting the voltage into an output, an integration circuit for integrating the output value Dvu of the A / D conversion circuit over a certain period Tc, and the number of times the voltage level detection circuit detects the voltage Vu within the certain period Tc , A divider that divides the integrated value of the integrating circuit by the count value of the counter, and a D / A converter circuit that converts the operation value of the divider into an analog value (Vu) and outputs the analog value. .

According to a seventh aspect of the present invention, in accordance with the fifth or sixth aspect of the present invention, the slice level SL is made lower than the black level Vb even if the fixed period Tc is not lengthened as in the one-field period, thereby providing a stable synchronization signal. The voltage level detection circuit detects a voltage equal to or higher than the threshold value Vt and equal to or lower than the set value Es among the detection voltages immediately after the rising of the clamped video signal after the detection of the detection voltage Vd. A voltage Vu is output, and the set value Es
Is set to a value lower than the peak level Vp of the copy guard signal Scg.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, the set value Es for detecting the black level is set higher than the black level Vb so that no video signal is included in the separated synchronization signal. , A voltage lower than a voltage (2 Vb−Vc) obtained by subtracting the clamp voltage Vc from a voltage twice as high as the black level Vb, and the slice level SL created by the voltage dividing circuit is set lower than the black level Vb.

According to a ninth aspect of the present invention, the slice level S is always stable in the fifth, sixth, seventh or eighth aspect.
In order to enable the synchronization signal to be extracted by L, the voltage dividing circuit is configured to hold the slice level SL created immediately before creating a new slice level SL.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a sync separation circuit according to the present invention. FIG. 1 shows a first embodiment of a sync separation circuit according to the present invention.
The same parts as in FIG. In FIG. 1, reference numeral 22 denotes a sync separation IC, which is composed of a clamp circuit 14, a voltage divider circuit 18, a slice circuit 20, and a sample hold circuit 24.

The clamp circuit 14 adjusts the lower end level of the composite video signal input via the coupling capacitor 12 to a predetermined clamp voltage Vc (constant DC voltage) and outputs the same, and outputs resistors R1 and R2 having the same resistance value. The voltage dividing circuit 18 connected in series creates a divided voltage of (Vu + Vd) / 2 based on the sampling voltages Vd and Vu held by the sample and hold circuit 24, and the slice circuit 20 is clamped by the clamp circuit 14. A level portion equal to or lower than the slice level SL of the synthesized video signal thus extracted is extracted and output as a synchronization signal.

The sample-and-hold circuit 24 samples the voltage immediately after the falling edge of the composite video signal clamped by the clamp circuit 14, and the sampling voltage Vd when the sampled value is equal to or less than a threshold value Vt (threshold voltage). After the sampling voltage Vd is held, the voltage immediately after the rising edge of the composite video signal clamped by the clamp circuit is sampled, and the sampling voltage Vu when this sampling value is equal to or more than the threshold value Vt and equal to or less than the set value Es is calculated. It is configured to hold. The sample hold circuit 24 is configured to continue holding the sampling voltages Vd and Vu held immediately before holding the new sampling voltages Vd and Vu. The threshold value Vt is set to a value higher than the clamp voltage Vc and lower than the black level Vb, and the set value Es represents a set value for black level detection set to 2Vb-Vc or less.

Next, the operation of FIG. 1 will be described with reference to FIG. (1) For convenience of description, of the composite video signal input via the coupling capacitor 12 and clamped to the clamp voltage Vc by the clamp circuit 14, the synchronizing signal Sd and the copy guard signal Scg are superimposed during the retrace period. Part is
It is assumed that the signal is as shown in FIG. In FIG. 2, S
v represents a part of the video signal, and Vp represents the peak level of the copy guard signal Scg.

(2-1) In the retrace period P1 in which the synchronizing signal Sd of the composite video signal in FIG. 2 is superimposed, the sample and hold circuit 24 sets the voltage Vd (= Vc) immediately after the falling of the synchronizing signal Sd. ) Is sampled and retained,
After holding the sampling voltage Vd, the synchronization signal Sd
Sampled and held at the voltage Vu (= Vb) immediately after the rising edge (the black circle in the figure is a sampling point).

(2-2) The voltage dividing circuit 18 includes the sampling voltages Vd and Vu held by the sample and hold circuit 24.
Based on the slice level SL (= (Vd + Vu) /
2) is created and output to the slice circuit 20. Vu = V
Since b and Vd = Vc, the slice level SL becomes (Vb + Vc) / 2 lower than the black level Vb. The slicing circuit 20 extracts a level portion equal to or lower than the slice level SL from the composite video signal clamped to the clamp voltage Vc and sets it as a synchronizing signal. Therefore, it is possible to separate stable equivalent signals without synchronizing disturbance.

(3-1) In the flyback period P2 in which the copy guard signal Scg of the composite video signal in FIG. 2 is superimposed, the sample hold circuit 24
The voltage Vd (= V) immediately after the fall of the first pulse of cg
c) is sampled and held, and after holding the sampling voltage Vd, the voltage immediately after the rising of the second pulse of the copy guard signal Scg is sampled (the x mark in the figure is a sampling point). The sampling voltage is not held because it has a peak level Vp higher than the set value Es. Similarly, the voltage immediately after the rising of the third, fourth, and fifth pulses of the copy guard signal Scg is sampled (the mark x in the figure is a sampling point), but the peak level Vp is higher than the set value Es. Do not hold it. As described above, in the flyback period P2, the sample hold circuit 24 outputs the new sampling voltage Vd.
And Vu are not held, so that the sampling voltages Vd and Vu held in the immediately preceding retrace period P1 are held.

(3-2) The voltage dividing circuit 18 controls the flyback period P1
At the slice level SL based on the sampling voltages Vd and Vu held by the sample and hold circuit 24.
(= (Vu + Vd) / 2) to create the slice circuit 20
Output to As described in the above (2-2), Vu =
Since Vb and Vd = Vc, the slice level SL becomes (Vb + Vc) / 2 lower than the black level Vb. The slicing circuit 20 extracts a level portion equal to or lower than the slice level SL from the composite video signal clamped to the clamp voltage Vc and sets it as a synchronizing signal. Therefore, it is possible to separate stable equivalent signals without synchronizing disturbance.

(4) A flyback period P3 immediately after the fifth (last) pulse of the copy guard signal Scg in the composite video signal of FIG. 2 (a period immediately before the video signal Sv appears).
Then, the sample-and-hold circuit 24 determines that the retrace period P3
Vu immediately after the first rise of the composite video signal at
(= Vb) is sampled and held. When new sampling voltages Vd and Vu are held by this sampling, the sampling voltages Vd and Vu held during the flyback period P1 and continued during the flyback period P2 are replaced with new sampling voltages Vd and Vu. , Voltage dividing circuit 1
8, the slice level SL (= (Vd + Vu) /
2) is created. Also in this case, Vu = Vb and Vd = Vc, as described in the above (2-2), and the slice level SL is lower than the black level Vb (Vb + Vc) / 2.
Then, the slice circuit 20 extracts a level portion equal to or lower than the slice level SL from the composite video signal and uses it as a synchronizing signal. Therefore, a stable equivalent signal without synchronizing disturbance can be separated.

In the embodiment shown in FIG. 1, the set value Es for detecting the black level is set to a value lower than (2Vb-Vc), and the slice level SL created by the voltage divider becomes lower than the black level Vb. Although the video signal is not included in the synchronization signal extracted by the slice circuit at all, the present invention is not limited to this. The set value Es for detecting the black level is lower than the peak level Vp of the copy guard signal Scg. It can also be used for those set to values.

FIG. 3 shows a second embodiment of the synchronization separating circuit according to the present invention. The same parts as those in FIG. In FIG. 3, reference numeral 26 denotes a sync separation I
C, the sync separation IC 26 includes the clamp circuit 14, the voltage dividing circuit 18, the slice circuit 20, the sample and hold circuit 24a, and the peak clipper 28.

The peak clipper 28 is input via the coupling capacitor 12, and the clamp circuit 14 cuts off a signal of a set value Esa or more from the composite video signal whose lower end level is adjusted to a predetermined clamp voltage Vc. ,
It is configured to output only a signal lower than the set value Esa. The sample hold circuit 24a samples the voltage immediately after the falling of the output signal of the peak clipper 28, holds the sampling voltage Vd when the sampled value is equal to or lower than the threshold value Vt, and holds the sampling voltage Vd after holding the sampling voltage Vd. The voltage immediately after the rising of the output signal of the peak clipper 28 is sampled, and the sampling voltage Vu when the sampling value is equal to or higher than the threshold value Vt is held. The sample hold circuit 24a is configured to continue holding the sampling voltages Vd and Vu held immediately before holding the new sampling voltages Vd and Vu. For this reason, the sample-and-hold circuit 24a transmits, to the sample-and-hold circuit 16 in the conventional synchronous separation IC 10 shown in FIG. 5, "the sampling voltage held immediately before holding the new sampling voltages Vd and Vu. The function of "continue holding Vd and Vu" is added.

Next, the operation of FIG. 3 will be described. (1) The peak clipper 28 is a signal component higher than the set value Esa set for black level detection, of the composite video signal input through the coupling capacitor 12 and clamped by the clamp circuit 14 to the clamp voltage Vc. Is truncated, and outputs only signal components equal to or smaller than the set value Esa. This set value Es is set to a voltage lower than 2Vb-Vc.

(2) Synchronization signal Sd of composite video signal
In the flyback period P1 in which the voltage Vd (= Vd) is superimposed on the voltage Vd (= V
c) is sampled and held, and after holding the sampling voltage Vd, the voltage Vu (= Vb) immediately after the rising of the synchronizing signal Sd is sampled and held, and the voltage dividing circuit 18 is based on the sampling voltages Vd and Vu. The slice level SL (= (Vd + Vu) / 2) is created and output to the slice circuit 20. Vd = Vc, Vu = Vb
Therefore, the slice level SL is (Vb + Vc) / 2 lower than the black level Vb. Since the slice circuit 20 extracts a level portion equal to or lower than the slice level SL from the composite video signal clamped by the clamp circuit 14 and uses it as a synchronization signal, it is possible to separate stable equivalent signals without synchronization disturbance.

(3) In the flyback period P2 in which the copy guard signal Scg of the composite video signal is superimposed, signal components higher than the set value Esa are cut off by the peak clipper 28, and only the composite video signal equal to or less than the set value Esa Is input to the sample and hold circuit 24a, so that the voltage V sampled and held by the sample and hold circuit 24a
d and Vu become Vc and Esa, and this Esa is 2Vb−
It is set to a value lower than Vc. Therefore, in the flyback period P2, the slice level S
L becomes lower than the black level Vb as shown in the following equation (2). SL = (Vd + Vu) / 2 = (Vd + Esa) / 2 <(2Vb−Vc + Vc) / 2 = Vb (2) Since the level portion is extracted and used as a synchronization signal, it is possible to separate stable equivalent signals without synchronization disturbance.

In the embodiment shown in FIGS. 1 and 3, the sample and hold circuit keeps holding the sampling voltages Vd and Vu held immediately before, until holding the new sampling voltages Vd and Vu. Although the synchronization signal can be separated based on the stable slice level SL, the present invention is not limited to this.

FIG. 4 shows a third embodiment of the sync separation circuit according to the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and their description is omitted. In FIG. 4, 14 is a clamp circuit, 18a is a voltage divider circuit, 20 is a slice circuit, 30 is a voltage level detection circuit that detects voltages Vd and Vu, and 32 is a fixed period Tc of the detected voltage Vu (for example, one field period).
Is an average value calculation circuit for calculating an average value (Vu) in the above. The voltage dividing circuit 18a receives a vertical synchronizing signal (for a certain period T
c), the voltage Vd taken in for each input
(Vu), the divided voltage (Vd + (Vu))
/ 2 is generated and output, and the holding is continued until a new divided voltage (Vd + (Vu)) / 2 is determined in the next predetermined period Tc.

The voltage level detection circuit 30 receives an input via the coupling capacitor 12 and
Detects the voltage Vd that is equal to or lower than the threshold value Vt among the voltages immediately after the falling of the composite video signal whose lower end level is adjusted to the predetermined clamp voltage Vc, and is clamped by the clamp voltage Vc after the detection of the voltage Vd. It is configured to detect and output a voltage Vu equal to or higher than the threshold value Vt among the voltages immediately after the rise of the synthesized video signal. The voltage level detection circuit 30 is further configured to output a detection signal K every time the voltage Vu is detected.

The average value calculating circuit 32 includes an A / D (analog / digital) converting circuit 34 for converting the detected voltage Vu of the voltage level detecting circuit 30 into a digital value Dvu and outputting the digital value Dvu; 34, an integration circuit 36 for integrating the output value Dvu over a certain period Tc (for example, one field period), and the number of times the detection voltage Vu is detected based on the detection signal K output from the voltage level detection circuit 32 within the certain period Tc. , A divider 40 for dividing the integrated value of the integrating circuit by the count value of the counter, and an analog value (V
u), and a D / A (digital / analog) conversion circuit 42 for outputting the converted signal. The counter 3
8 and the divider 40 are configured such that the operation value is cleared by the vertical synchronization signal. The integrating circuit 36 includes an adder 44 and a register 46. The adder 44 is configured to store the output value Dvu of the A / D conversion circuit 34 and the register 46.
The register 46 is configured to set the added value of the adder 44 and clear the set value by the vertical synchronizing signal.

Next, the operation of FIG. 4 will be described. For convenience of description, the certain period Tc is set to one field period corresponding to a vertical synchronization signal as a clear signal. When the fixed period Tc is other than one field period, the clear signal (vertical synchronization signal in FIG. 4) is a corresponding signal other than the vertical synchronization signal (for example, a signal having a pulse cycle of Tc). (1) The voltage level detection circuit 30 is inputted via the coupling capacitor 12 and based on the composite video signal clamped by the clamp circuit 14, the falling voltage Vd falling below the threshold Vt and the falling voltage Vt falling above the threshold Vt. A rising voltage Vu is detected, and a detection signal K is output each time the voltage Vu is detected.

(2) In the average value calculation circuit 32, the A / D conversion circuit 34 converts the detection voltage Vu into a digital value Dvu, and the integration circuit 36 integrates the output value Dvu over one field period (an example of Tc). , The counter 38 counts the number of times the detection voltage Vu is detected in one field period,
The divider 40 divides the integrated value by the count value, and the D / A conversion circuit 42 converts the operation value of the divider 40 into an analog value (Vu) and outputs it. In one field period, the number of pulses of the copy guard signal Scg is so small as to be insignificant compared to the number of pulses of the synchronization signal Sd (for example, a horizontal synchronization signal). The detected voltage (Vu) becomes a value close to the black level Vb, which is much lower than the peak level Vp of the copy guard signal Scg.

(3) The voltage dividing circuit 18a compares the voltage (Vu) calculated by the average value calculating circuit 32 with the voltage level detecting circuit 3
0 based on the voltage Vd detected at 0 (Vu)
+ Vd) / 2, and outputs this to the slice circuit 20 as the slice level SL. Since this voltage (Vu) is a value close to the black level Vb as described in (2) above,
The slice level SL becomes lower than the black level Vb. Based on such a slice level SL, the slice circuit 20
Extracts a synchronization signal, so that stable synchronization separation can be performed without causing a synchronization disorder even when an input of a video signal on which the copy guard signal Scg is superimposed.

In the embodiment shown in FIG. 4, the voltage dividing circuit keeps holding the slice level SL created immediately before until a new slice level SL is created, and always based on the stable slice level SL. Although the synchronization signal can be separated, the present invention is not limited to this.

In the embodiment shown in FIG. 4, the average value calculation circuit is composed of an A / D conversion circuit, an accumulation circuit, a counter, a divider and a D / A conversion circuit, but the present invention is not limited to this. Instead, any device may be used as long as it calculates the average value (Vu) of the detection voltage Vu of the voltage level detection circuit during the fixed period Tc.

In the embodiment shown in FIG. 4, after detecting the voltage Vd, the voltage level detection circuit detects and outputs the voltage Vu which is equal to or higher than the threshold value Vt among the voltages immediately after the rise of the composite video signal. However, the present invention is not limited to this. After detecting the voltage Vd, the voltage Vu which is equal to or higher than the threshold value Vt and equal to or lower than the set value Es (or Esa) among the voltages immediately after the rising edge of the composite video signal. It is also possible to use a device configured to detect and output a. When this set value is Es (a value lower than the peak level of the copy guard signal), the fixed period Tc can be made shorter than that of the embodiment of FIG. 4, and Esa (2Vb−V
(value lower than c), the fixed period Tc can be further shortened, and the separated synchronization signal does not include any video signal.

[0043]

According to the first aspect of the present invention, there is provided a synchronization separating circuit comprising:
As described above, the clamp circuit, sample and hold circuit,
In a retrace period in which a copy guard signal Scg of the video signal is superimposed, including a voltage dividing circuit and a slice circuit,
Sampling voltage Vu held by sample and hold circuit
Is equal to or higher than the threshold value Vt and equal to or lower than the set value Es (normally, the black level Vb). Since the set value Es is set to a value lower than the peak level Vp of the copy guard signal, the sampling voltage Vu is
cg does not reach the peak level Vp. For this reason,
The slice level SL created by the voltage divider circuit is the black level Vb
The voltage becomes lower (for example, (Vb + Vc) / 2), and stable synchronization separation can be performed without causing synchronization disturbance even for the input of the video signal on which the copy guard signal Scg is superimposed.

According to a second aspect of the present invention, in the first aspect of the present invention, the set value Es for detecting the black level is increased from the voltage higher than the black level Vb and twice the black level Vb to the clamp voltage Vc.
, The voltage is lower than the voltage (2Vb-Vc), so that the slice level SL created by the voltage dividing circuit is surely lower than the black level Vb so that no video signal is included in the separated synchronization signal. can do.

According to a third aspect of the present invention, there is provided a synchronous separation circuit comprising a clamp circuit, a peak clipper, a sample and hold circuit,
A voltage divider circuit and a slice circuit are provided, and a signal having a value equal to or greater than the set value Esa of the video signal is truncated by the peak clipper and input to the sample-and-hold circuit. The sampling voltage Vu held by the hold circuit is configured to be equal to or higher than the threshold value Vt and equal to or lower than the set value Esa. Since the set value Esa is set to a voltage lower than (2Vb−Vc), the slice level SL created by the voltage divider circuit is lower than the black level Vb (for example, (Vb + Vc).
c) / 2), and no synchronization disorder is caused even when the video signal on which the copy guard signal Scg is superimposed is input.
Stable synchronization separation can be performed.

According to a fourth aspect of the present invention, in the first, second or third aspect of the present invention, the sampling and holding circuit holds the sampling voltages Vd and Vu held immediately before until the sample and hold circuit holds the new sampling voltages Vd and Vu. Since the holding is continued, the synchronization signal can be always taken out with the stable slice level SL.

According to a fifth aspect of the present invention, there is provided a synchronization separating circuit comprising a clamp circuit, a voltage level detecting circuit, an average value calculating circuit, a voltage dividing circuit and a slice circuit, and the average value calculating circuit detects a voltage detected by the voltage level detecting circuit. The average value (Vu) of Vu during a certain period Tc is calculated, and the voltage dividing circuit calculates the average value (Vu).
u) and the detection voltage Vd of the voltage level detection circuit,
The slice level SL of the slice circuit (SL = ((Vu)
+ Vd) / 2), the voltage Vu detected by the voltage level detection circuit becomes the black level Vb and the peak level of the copy guard signal Scg during the flyback period in which the copy guard signal Scg is superimposed. Vp, but by setting the fixed period Tc to an appropriate value (for example, one field period), the number of pulses of the copy guard signal Scg becomes equal to the number of pulses of the synchronization signal Sd (for example, the horizontal synchronization signal) within the fixed period Tc. It can be reduced so that it is not a problem compared to the number. Therefore, the voltage (Vu) averaged by the average value calculating circuit over a certain period Tc becomes a value close to the black level Vb which is much smaller than the peak level Vp of the copy guard signal Scg, and the slice level SL created by the voltage dividing circuit becomes black. A voltage lower than the level Vb (for example, (V
b + Vc) / 2), and stable synchronization separation can be performed without causing synchronization disturbance even for the input of the video signal on which the copy guard signal Scg is superimposed.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the average value calculating circuit includes an A / D conversion circuit, an integrating circuit, a counter, a divider, and a D / A conversion circuit, and uses a digital circuit. The averaged voltage (V
Since u) is obtained, the voltage (Vu) can be calculated more accurately.

According to a seventh aspect of the present invention, in the fifth or sixth aspect of the present invention, the voltage level detecting circuit detects the detection voltage Vd after the detection of the detection voltage Vd and immediately after the rise of the video signal.
A voltage equal to or higher than the threshold value Vt and equal to or lower than the set value Es for detecting the black level is output as the detection voltage Vu. Since the set value Es is set to a value lower than the peak level Vp of the copy guard signal Scg, Detection voltage V of detection circuit
u can always be lower than the peak level Vp of the copy guard signal Scg. For this reason, a stable synchronization signal can be obtained without lengthening the constant period TC for obtaining the average value so much, and stable slice separation can be performed by setting the slice level SL lower than the black level Vb. .

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, the set value Es for black level detection is increased from a voltage higher than the black level Vb and twice the black level Vb to the clamp voltage Vc.
Since the set value Esa is lower than the voltage (2Vb−Vc) obtained by subtracting the above, the slice level SL created by the voltage divider circuit is set lower than the black level Vb so that no video signal is included in the separated synchronization signal. can do.

According to a ninth aspect of the present invention, in the invention of the fifth, sixth, seventh or eighth aspect, the voltage dividing circuit holds the slice level SL created immediately before until a new slice level SL is created. Therefore, the synchronization signal can be always taken out with the stable slice level SL.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a sync separation circuit according to the present invention.

FIG. 2 is a waveform diagram illustrating the operation of FIG.

FIG. 3 is a block diagram showing a second embodiment of the sync separation circuit according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of a sync separation circuit according to the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform diagram illustrating an operation when a copy guard signal is not superimposed in FIG.

FIG. 7 is a waveform diagram illustrating an operation when a copy guard signal is superimposed in FIG.

[Explanation of symbols]

10, 22, 26: Sync separation IC, 12: Coupling capacitor, 14: Clamp circuit, 16, 24,
24a: sample and hold circuit, 18, 18a: voltage divider circuit, 20: slice circuit, 28: peak clipper, 30: voltage level detection circuit, 32: average value calculation circuit, 34: A / D (analog / digital) conversion circuit 36, an integrating circuit, 38, a counter, 40, a divider, 42, a D / A (digital / analog) conversion circuit, 44, an adder, 46, a register, Es, Es
a: a set value for detecting a black level; P1: a blanking period in which the synchronization signal Sd is superimposed; P2: a copy guard signal Sc
a blanking period in which g is superimposed, P3... a blanking period before the start of the video signal Sv after the lapse of the period P2 among the blanking periods,
Scg: copy guard signal, Sd: synchronization signal, S
L, SL1, SL2: slice level, Sv: video signal, Vb: black level, Vc: clamp voltage, Vd
... Sampling voltage held immediately after falling (lower detection voltage in FIG. 4), Vp... Copy guard signal Scg
Vt: threshold value (threshold voltage), Vu: held sampling voltage immediately after rising (higher detection voltage in FIG. 4).

Claims (9)

[Claims] 1. A clamp circuit for adjusting the lower end level of a video signal on which a synchronization signal is superimposed to a clamp voltage Vc, and a voltage immediately after a fall of the video signal clamped by the clamp circuit is sampled, and the sampling value is a threshold. Value Vt
After the sampling voltage Vd is held, the voltage immediately after the rising of the clamped video signal is sampled after holding the sampling voltage Vd, and the sampled value is equal to or larger than the threshold value Vt and the set value Es (Es is a copy guard) A sample-and-hold circuit for holding the sampling voltage Vu when the signal level is equal to or less than the black level detection value set to a value lower than the signal peak level, and the sampling voltages Vu and Vd held by the sample-and-hold circuit
Based on the slice level SL (SL = (Vu + Vd)
/ 2), and a slice circuit that extracts a level portion equal to or lower than a slice level SL from the video signal clamped by the clamp circuit and uses it as a synchronization signal. Sync separation circuit. 2. The black level detection set value Es is higher than the black level Vb and lower than a voltage (2Vb-Vc) obtained by subtracting the clamp voltage Vc from a voltage twice the black level Vb. Or the synchronization separation circuit according to 2. 3. A clamp circuit for adjusting the lower end level of a video signal on which a synchronizing signal is superimposed to a clamp voltage Vc, and a set value Es of the video signal clamped by the clamp circuit.
a (Esa is higher than the black level Vb, and 2
A voltage obtained by subtracting the clamp voltage Vc from the doubled voltage (2 Vb−
Vc) a peak clipper that cuts off a signal equal to or higher than a set value set to a voltage lower than Vc) and outputs a voltage, and samples a voltage immediately after the falling of the output signal of the peak clipper,
The sampling voltage Vd when the sampling value is equal to or lower than the threshold value Vt is held. After holding the sampling voltage Vd, the voltage immediately after the rising of the output signal of the peak clipper is sampled. And a voltage divider circuit for generating a slice level SL (SL = (Vd + Vu) / 2) based on the sampling voltages Vd and Vu held by the sample / hold circuit. A synchronizing separation circuit, comprising: a slice circuit that extracts a level portion equal to or lower than a slice level SL from the video signal clamped by the clamp circuit and uses it as a synchronizing signal. 4. The synchronous circuit according to claim 1, wherein the sample hold circuit keeps holding the sampling voltages Vd and Vu held immediately before holding the new sampling voltages Vd and Vu. Isolation circuit. 5. A clamp circuit for adjusting a lower end level of a video signal on which a synchronizing signal is superimposed to a clamp voltage Vc, and a voltage lower than a threshold value Vt of a voltage immediately after a fall of the video signal clamped by the clamp circuit. A voltage level detection circuit for detecting Vd and detecting a voltage Vu that is equal to or higher than a threshold value Vt of the voltage immediately after the rising of the clamped video signal after the detection of the voltage Vd; An average value calculation circuit for calculating an average value (Vu) of the voltage Vu during a certain period Tc; and a slice level SL based on the average value (Vu) calculated by the average value calculation circuit and the detection voltage Vd of the voltage level detection circuit.
A voltage dividing circuit for generating (SL = ((Vu) + Vd) / 2), and a slice circuit for extracting a level portion equal to or lower than a slice level SL from the video signal clamped by the clamp circuit and using the same as a synchronization signal. A synchronization separation circuit, comprising: 6. An average value calculating circuit converts an detected voltage Vu of a voltage level detecting circuit into a digital value Dvu and outputs the digital value Dvu, and an output value Dvu of the A / D converting circuit.
, A counter that counts the number of times the voltage level detection circuit detects the voltage Vu within the fixed period Tc, and divides the integrated value of the integration circuit by the count value of the counter. 6. The synchronization separation circuit according to claim 5, comprising: a divider; and a D / A conversion circuit that converts an operation value of the divider into an analog value (Vu) and outputs the analog value. 7. A voltage level detection circuit comprising: a threshold value Vt or more of a set value Es (Es is a peak level of a copy guard signal) of a detection voltage immediately after a rising edge of a clamped video signal after detection of a detection voltage Vd. A voltage equal to or lower than the set value for black level detection set to a lower value)
7. The synchronization separation circuit according to claim 5, wherein the synchronization separation circuit outputs the signal. 8. The black level detection set value Es is higher than the black level Vb and lower than a voltage (2Vb-Vc) obtained by subtracting the clamp voltage Vc from a voltage twice the black level Vb. Synchronous separation circuit as described. 9. The synchronization separation circuit according to claim 5, wherein the voltage dividing circuit holds the slice level SL created immediately before creating a new slice level SL.