KR920001109B1 - Vdp still signal detecting circuit - Google Patents

Abstract

The circuit counts main clock signals and compares them with vertical synchronous signals for accurate COMB filtering to detec VDP signal. The circuit comprises a synchronous signl extractor (1) for extracting vertical, horizontal, and color synchronous signal from video signal, a phase difference detector (4) for discriminating normal signal or VTR signal by comparing them with clock pulses generated by a horizontal and a color synchronous voltage generator (2,3), a VDP detector (5) for discriminating VDP halt signal by comparing clock pulse with 28 MHz generated by the color synchronous voltage generator (3) with vertical synchronous signal, an AND gate for identifying NTSC signal when states of output signals of the detectors (4,5) are high and a dividing circuit (7) for dividing the brightneww signal and the color signal by the output signal of the AND gate.

Description

VDP stop signal detection circuit

1 is a block diagram of a circuit according to the present invention.

2 is a detailed block diagram of the VDP detection circuit of FIG.

3 is a waveform diagram of a second diagram in the case of a normal NTSC signal.

4 is an operational waveform diagram of FIG. 2 at the time of VDP stop signal.

* Explanation of symbols for the main parts of the drawings

1: Synchronization and color synchronization signal separation circuit 2: Horizontal synchronization voltage control oscillation circuit (HVCO)

3: Color synchronizing voltage controlled oscillation circuit (BVCO) 4: Phase difference detection circuit

5: VDP stop signal detection circuit 6: AND gate

7: luminance and color signal separation circuit 8: counter

9: D flip-flop 10: Phase detector

11: low pass filter 12: reference voltage generator

13: comparator

The present invention relates to a circuit for detecting a VDP stop signal, and more particularly to a circuit capable of detecting a VDP signal capable of accurately separating a luminance signal and a color signal.

In general, a method of separating a luminance signal and a color signal includes a method of using a comb filter to separate a frequency. In the method of separating the frequency, the frequency characteristics of the color signal are deteriorated by simply separating the frequency and separating the luminance signal and the color signal by using a trap or a band pass filter. In addition, by using a filter having an attenuation characteristic using a comb filter, it is excellent in separating luminance signal and color signal from National Television System Committee (NTSC) signal.

(f_sc: 색부반송파 주파수, fH : 수평동기 주파수)를 만족하면 라인 콤필터링(Line Comb Filtering)이나 프레임 콤필터링(Frame Comb Filtering)하여 휘도신호와 색신호를 분리할 수 있었다. 그러나 VTR 신호에 있어서 색부반송파 주파수와 수평동기 주파수의 상관관계가 상기 식을 만족할 수 없으므로 휘도신호와 색신호를 분리함에 있어서 콤필터를 사용하지 않고 주파수를 분리하여 행하였다.In the existing NTSC signal

When (f _sc : color carrier frequency, fH: horizontal synchronization frequency) is satisfied, the luminance signal and the color signal can be separated by line comb filtering or frame comb filtering. However, since the correlation between the color carrier frequency and the horizontal synchronization frequency in the VTR signal cannot satisfy the above expression, the frequency is separated without using a comb filter to separate the luminance signal and the color signal.

의 관계식을 성립하지만 수직동기 신호가 상기 VDP의 정지화면이 정상적인 NTSC신호보다 140nSec가 길기 때문에 프레임 콤필터링을 할 수 없는 문제점이 있었다.That is, if the difference between the two signals is not detected by comparing the frequency of 28 MHz with a predetermined period locked to the horizontal synchronization frequency, for example, 28 MHz and the 28 MHz frequency locked to the color synchronization signal, it is recognized as a normal NTSC signal. When the difference between the two signals is detected, the signal is recognized as a VTR signal. Therefore, the general NTSC signal and the VTR signal are separated by the comb filtering and the frequency, respectively, to separate the luminance signal and the color signal. However, in the case of still images of VDP (Video Disc Player), the horizontal synchronization frequency and the color carrier frequency

However, the vertical synchronization signal has a problem that frame comb filtering is not possible because the VDP still picture is 140 nSec longer than a normal NTSC signal.

Accordingly, an object of the present invention is to provide a circuit capable of detecting a VDP signal by counting a main clock and comparing it with a vertical synchronization signal for accurate comb filtering.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a circuit according to the present invention, in which a synchronization and color synchronization signal separation circuit 1 for separating horizontal, vertical and color synchronization signals from an input composite video signal and a frequency of 28 MHz locked to the horizontal synchronization signal are shown in FIG. A horizontal synchronous voltage generating circuit (2) for generating a clock pulse having a signal; a color synchronous voltage generating circuit (3) for generating a clock pulse having a frequency of 28 MHz locked to the color synchronous signal; A phase difference detection circuit 4 for comparing a clock pulse having a frequency of 28 MHz generated by the generation circuits 2 and 3 to determine whether it is a normal NTSC signal or a VTR signal, and the color synchronization voltage generation circuit ( A VDP detecting circuit 5 for discriminating whether it is a normal NTSC signal or a VDP stop signal by comparing a clock pulse having a frequency of 28 MHz and a vertical synchronizing signal generated in 3), and the phase difference detecting circuit 4 and VDP detection On the circuit (5) The AND gate 6 recognizes a normal NTSC signal only when the signals output from the high signal are all high, and the luminance signal and the color signal are controlled by controlling the separation method of the luminance signal and the color signal according to the output signal of the AND gate 6. It consists of a luminance and color signal separation circuit 7 for separating the.

FIG. 2 is a detailed block diagram of the VDP signal detection circuit 5 of FIG. 1, in which the VDP signal detection circuit 5 generates a predetermined frequency generated by the color synchronizing voltage oscillation circuit 3, for example, a frequency of 28 MHz. The counter 8 outputs a vertical synchronous signal for a predetermined time, for example, 140 nSec longer than the vertical synchronous signal of a normal NTSC signal by counting a clock pulse, and a D flip-flop so that the duty of the input signal is 50%. 9), a phase detector 10 for detecting phases of the signals output from the counter 8 and the D flip-flop 9, and the outputs of the phase detector 10 are filtered to convert a predetermined DC value. A low pass filter 11, a variable reference voltage generator 12, and a comparator 13 for comparing the output of the low pass filter 11 with the output of the reference voltage generator 12.

3 and 4 are operational waveform diagrams of FIG. 2, where FIG. 3 shows normal NTSC signals, and FIG. 4 shows when the VDP stop signal is applied. (3a) and (4a) are the vertical synchronization signals, (3b) and (4b) are the signals of the output terminal Q of the D flip-flop 9, and (3c) and (4c) are the D-flop 9 (3d) and (4d) are the output signals of the counter 8, and (3e) and (4e) are the output signals of the phase detector (10).

Hereinafter, the detailed operation of the circuit according to the present invention will be described.

의 관계가 성립되므로 상기 신호들에 각각 로킹된 28MHz는 차이가 없어 “하이” 상태로 출력하며, VTR 신호일때에는 상기 신호들의 차이가 검출된 “로우” 상태로 출력한다. 상기 위상차분 검출회로(4)에서 “로우” 상태의 신호를 출력하면 앤드게이트(6)를 거쳐 휘도 및 색신호 분리회로(7)에 입력된다. 따라서 휘도 및 색신호 분리회로(7)는 주파수 분리를 하여 상기 VTR 신호를 휘도신호와 색신호로 분리한다. 그러나 상기 VDP정지신호도

의 식을 만족하기 때문에 위상차분 검출회로(4)에서 “하이” 상태의 신호를 출력하게 되면 상기 단자(20)를 통해 입력되는 복합 영상신호가 정상적인 NTSC신호인지 또는 VDP의 정지신호인지를 알 수 없게 된다. 그러나, 상기 VDP정지신호의 수직동기신호는 정상적인 NTSC신호의 그것보다 140nSec가 긴 신호이므로 휘도 및 색신호 분리회로(7) 프레임 콤필터링을 할 때에는 화소가 일치하지 않아 휘도신호와 색동기신호의 정확한 분리가 불가능하였다. 따라서, 상기 동기 및 색동기 분리회로(1)에서 발생된 수직동기신호는 VDP정지신호 검출회로(5)에 입력된다. 또한 상기 BVCO(3)에서 출력되는 28MHz의 주파수를 갖는 클럭펄스를 입력한다.Each clock pulse having a frequency of 28 MHz generated by the HVCO 2 and the BVCO 3 is input to the phase difference detection circuit 4. The phase difference detection circuit 4 compares two clocks having a frequency of 28 MHz to distinguish whether the signal is a normal NTSC signal, a VDP stop signal, or a VTR signal. In case of normal NTSC signal and VDP stop signal, horizontal sync signal and color sync signal are

Since the relationship is established, each of the 28 MHz locked to the signals is outputted in the “high” state without a difference, and when the VTR signal is output in the “low” state where the difference between the signals is detected. When the phase difference detection circuit 4 outputs a signal in the "low" state, it is input to the luminance and color signal separation circuit 7 via the AND gate 6. Therefore, the luminance and color signal separation circuit 7 performs frequency separation to separate the VTR signal into a luminance signal and a color signal. However, the VDP stop signal also

When the phase difference detection circuit 4 outputs the signal of the “high” state, it is possible to know whether the composite video signal input through the terminal 20 is a normal NTSC signal or a VDP stop signal. There will be no. However, since the vertical synchronization signal of the VDP stop signal is 140 nSec longer than that of the normal NTSC signal, the luminance and color signal separation circuit (7) does not match the pixels when performing frame comb filtering. Was not possible. Accordingly, the vertical synchronization signal generated in the synchronization and color synchronization separation circuit 1 is input to the VDP stop signal detection circuit 5. Also, a clock pulse having a frequency of 28 MHz output from the BVCO 3 is input.

The VDP stop signal detection circuit 5 compares the vertical synchronization signal with a frequency of 28 MHz and detects whether or not the VDP stop signal is present. At this time, the signal output from the VDP stop signal detection circuit 5 is in the "high" state and is recognized as a normal NTSC signal, and in the "low" state, it is recognized as the VDP stop signal.

The VDP stop signal detection circuit 5 is configured as shown in FIG. 2, and the operation waveform diagram is shown in FIG.

First, a description will be given when a normal NTSC signal is applied.

A vertical synchronizing signal such as (3a) output from the synchronizing and color synchronizing separation circuit 1 is input to the D flip-flop 9 as a clock pulse through the terminal 30. In addition, a 28 MHz clock pulse output from the BVCO 3 via the terminal 25 is input to the counter 8 via the clock stage CLK. The counter 8 counts an input clock as 477754 clocks. Accordingly, a signal having a duty of 50% is output to the output terminal Q of the D flip-flop 9, as shown in (3b), and a signal such as (3c) in which the signal of (3b) is inverted to the sub output terminal Q. Is output.

The signal of (3c) is input to the reset stage RES of the counter 8, and also fed back to the D-flop 9 through the input stage D. (3c) outputted from the sub output terminal Q of the D flip-flop 9 also resets the counter 8 at the falling edge of the signal. If 477750 clock pulses are counted from this time, (3c) will also coincide with the rising edge of the signal. However, if four more clock pulses are counted from this point, 140 nSec will be delayed. Thus, the counter 8 outputs a signal such as (3d). The signals of the output stages 3c and 3d at the output stage Q and the counter 8 of the D flip-flop 9 are input to the phase detector 10, so that the phase detector 10 compares the signals. As shown in (3e), a signal whose phase is detected is output. The signal output from the phase detector 10 has a predetermined direct current value while passing through the low pass filter 11 and is compared with the output voltage of the reference voltage generator 12 which is variable in the comparator 13. Will print Therefore, since the signal of the "high" state output from the comparator 13 and the signal of the "high" state output from the phase difference detector 4 are input to the AND gate 6, the AND gate 6 is "high". And the normal NTSC signal is applied, the luminance and color signal separation circuit 7 is com-filtered to separate the luminance and color signals. However, when the VDP stop signal is applied, a vertical synchronization signal such as (4a) output from the synchronization and color synchronization separation circuit 1 is input to the D flip-flop 9 through the terminal 30.

The vertical synchronizing signal shown in (4a) above is 140 nSec delayed from the vertical synchronizing signal upon normal NTSC application. Accordingly, a signal having a duty of 50% is output from the output terminal Q of the D flip-flop 9 as shown in (4b), and a signal of inverted (4c) degree is output from the sub output terminal Q. The signal (4c) is input to the counter 8 through the reset RES, and is fed back through the input terminal D of the flip-flop 9.

Also, if a clock pulse having a frequency of 28 MHz output from the BVCO 3 is input to the counter 8 via the terminal 25, the counter 44 also resets the counter 8 at the falling edge of the signal. When 477754 clock pulses are counted, the counter 8 outputs a signal such as (4d). Therefore, when the signals of the degrees (4c) and (4d) are input to the phase detector 10, the phases of the signals (4c) and (4d) are the same as the phases of the signals. Output the status signal. Therefore, the signal output from the comparator 13 is always kept in a "low" state. Therefore, the signal of the "high" state from which the signal of the "low" state is output from the phase difference detector 4 is input to the AND gate 6, and thus the "low" state of the "low" state to the luminance and color signal separation circuit 7 A signal is input to recognize that the VDP stop signal is applied. Therefore, separation of the luminance signal and the color signal is performed by frequency separation.

As described above, the present invention has the advantage that the luminance signal and the color signal can be accurately separated by simple frequency separation such as the VTR signal during the VDP stop signal.

Claims (2)

A VDP stop signal detection circuit comprising: a synchronization and color synchronization signal separation circuit (1) for separating horizontal, vertical, and color synchronization signals from an input composite video signal, and a clock pulse having a predetermined frequency locked to the horizontal synchronization signal; A horizontal synchronous voltage generating circuit (2) for generating a signal, a color synchronous voltage generating circuit (3) for generating a clock pulse having a predetermined frequency locked to the color synchronous signal, and the horizontal and color synchronous voltage generating circuit (2). A phase difference detection circuit 4 for discriminating whether it is a normal NTSC signal or a VTR signal by comparing clock pulses having a predetermined frequency generated in (3), and a predetermined signal generated by the color synchronizing voltage generating circuit 3; A VDP detection circuit 5 for discriminating whether it is a normal NTSC signal or a VDP stop signal by comparing a clock pulse having a frequency of V and a vertical synchronization signal, and outputs from the phase difference detection circuit 4 and the VDP detection circuit 5. The separation method of the luminance signal and the color signal is controlled by controlling the separation method of the luminance signal and the color signal according to the output signal of the AND gate 6 and the AND gate 6 which recognize the normal NTSC signal only when all the signals are “high”. A VDP stop signal detection circuit comprising a luminance and color signal separation circuit (7). 2. The VDP stop signal detection circuit (5) according to claim 1, wherein the VDP stop signal detection circuit (5) counts a clock pulse having a predetermined frequency generated by the color synchronizing voltage oscillation circuit (3), and is vertical for a predetermined time longer than that of a normal NTSC signal. A counter 8 for outputting a synchronization signal, a D flip-flop 9 so that the duty of the selected signal input is 50%, and a phase of the signals output from the counter 8 and the D flip-flop 9 are detected A phase detector 10, a low pass filter 11 for filtering the output of the phase detector 10 and converting the output of the phase detector 10 into a predetermined DC value, a variable reference voltage generator 12, and the low pass filter 11. And a comparator (13) for comparing and outputting the output of the reference voltage generator and the output of the reference voltage generator (12).

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