JPH0628382B2 - Vertical sync signal generation circuit - Google Patents

Description

The present invention relates to a vertical synchronizing signal generating circuit used in an image display device such as a television receiver or an image processing device such as an image file system.

(B) Prior art In the image processing apparatus as described above, a method for creating an accurate and stable internal vertical synchronizing signal is disclosed in, for example, Japanese Patent Publication No.
As shown in Japanese Patent Publication No. -15595, a method of dividing a frequency signal of an integral multiple of the horizontal frequency to the vertical frequency to obtain the signal has been conventionally used.

However, such a method can be used for various image signals, such as a television receiver, a special playback VTR, especially the image file system and the image scanning speed conversion device described above.
Alternatively, it is not appropriate when handling an image signal from a computer or the like. This is because the frequency of the horizontal and vertical sync signals and the phase relationship between the two sync signals are not constant in each of the above image signals, so it is not possible to divide to the desired vertical frequency by the fixed division method, or This is because it may not be possible to accurately capture the external vertical synchronization signal input via the gate opened and closed by the circular output.

Therefore, as a simple alternative to this method, it is conceivable to take in an external vertical synchronizing signal at the timing of a reference signal of a constant phase and use the signal obtained thereby as an internal vertical synchronizing signal. However, in this way, in the method of simply capturing and synchronizing at the timing of the reference signal of a constant phase,
When the leading edge of the external vertical synchronizing signal is at a position very close to the timing of the reference signal, the internal vertical synchronizing signal thus obtained has 1 of the reference signal due to the phase fluctuation of the leading edge of the vertical synchronizing signal. Phase fluctuations of the period width occur. Such a phenomenon is particularly remarkable when an external vertical synchronizing signal separated from a 2: 1 interlaced television composite video signal is input. This is because, in the external vertical sync signal as described above, the signal waveform immediately before the vertical sync signal part in the composite video signal differs between the odd field and the even field, and the video signal part is shifted to the sync signal level. This is because the so-called “video-in sync” is very likely to cause the above-mentioned “fluctuation” of the leading edge. Therefore, this method cannot be applied to the above-described image processing apparatus that requires a stable internal vertical synchronizing signal.

(C) Problems to be Solved by the Invention In the present invention, it is possible to deal with various external vertical sync signals having different vertical frequencies or phase relationships with the horizontal sync signal.
Moreover, it is an object of the present invention to provide a vertical synchronization signal generation circuit capable of generating a stable and accurate internal vertical synchronization signal with respect to the phase fluctuation of the vertical synchronization signal.

(D) Means for Solving the Problems The present invention is directed to an oscillator that generates a signal having a horizontal synchronizing signal frequency n times (n is an integer) synchronized with an external horizontal synchronizing signal, and an oscillation signal obtained from the oscillator. And an internal vertical synchronizing signal generating circuit which generates an internal vertical synchronizing signal based on an external vertical synchronizing signal, in a horizontal synchronizing signal frequency based on an oscillation signal from the oscillator. A reference signal generating means for generating a signal and an external vertical synchronizing signal are fetched by any one of the first and second reference signals, the external vertical synchronizing signal is synchronized with the reference signal, and then supplied to the counter. The conversion means, the phase comparison means for comparing the phase of the reference signal selected from the first and second reference signals with the external vertical synchronizing signal, and the phase difference by the phase comparison means. A vertical synchronizing signal generating circuit comprising: means for switching the reference signal supplied to the synchronizing means when it is detected that there is no such signal.

(E) Operation According to the above configuration, the external vertical synchronizing signal is synchronized with the reference signal at a timing which is always sufficiently separated from the leading edge portion thereof, so that the influence of the phase fluctuation of the leading edge portion is eliminated. .

(F) Embodiment FIG. 1 shows an embodiment of the vertical synchronizing signal generating circuit of the present invention. In the figure, (1) is an input terminal for an external vertical synchronizing signal (hereinafter referred to as an external V signal), (2) is a 1/2 frequency dividing circuit for the V signal, and (3) is a frequency dividing output thereof. AND gate that receives the signal and the V signal as an input, and (4) a first synchronization composed of a D flip-flop or the like that takes in the output signal at the timing of an internal horizontal synchronization pulse (hereinafter referred to as an internal H pulse) described later. Circuit. (5) is a second synchronization circuit which can have the same configuration as the first synchronization circuit and takes in its output signal by another internal H pulse.
(6) is a first counter that counts the number of internal H pulses in one cycle of the output signal, and (7) is the output signal of the second synchronizing circuit (5) while the count result is preset. A second counter that is reset,
(8) is an output terminal from which the internal vertical synchronizing signal is derived.

Further, (9) is an integral multiple of the standard horizontal frequency f _H , that is, nf
A VCO (voltage controlled oscillator) whose center frequency is _H (where n ≠ 1), and (10) has a frequency f _H from its output signal.
A frequency dividing circuit for generating two reference signals whose phases are different from each other, that is, a first second internal H pulse and a 2f _H pulse, (1
1) is a first phase detection circuit for phase-detecting the second internal H pulse and the external H pulse input to the terminal (12), and these constitute a PLL (phase locked loop) circuit (13). There is. (14) is a selector circuit that introduces the first and second internal H pulses and selects either one of them according to the output of the flip-flop (15), and (16) selects the selected H pulse as the first A window pulse generation circuit that outputs a pulse to the synchronization circuit (4) and widens the pulse width of the pulse to the front and back, (1
7) is a second phase detection circuit for detecting the phase difference between the wide pulse and the output signal of the AND gate (3), and the flip-flop (15) is inverted by this output. . Incidentally, (18) is an output terminal for the internal H pulse.

The operation of such an embodiment will be described with reference to the signal waveform diagrams of FIGS. 2 and 3. Now, assuming that the external V signal (a) having the field period (1V) shown in FIG. 2 is input to the terminal (1), the output signal of the 1/2 frequency dividing circuit (2) becomes the same figure (b). Then, the output signal of the AND gate (3) is as shown in FIG. This signal (c) is taken in at the leading edge timing of the internal H pulse output from the window pulse generating circuit (16) in the next first synchronizing circuit (4). Therefore,
Now, as the internal H pulse, the second of the first and second internal H pulses (d) and (e) input to the selector circuit (14).
Assuming that the internal H pulse (e) is output, the output signal of the first synchronizing circuit (4) is as shown in FIG. Then, since this output signal (f) is taken in at the leading edge timing of the first internal H pulse (d) in the second synchronizing circuit (5), the output signal is the same (g) in FIG.
In this way, the internal vertical synchronizing signal of 2V cycle, that is, the frame cycle is obtained.

On the other hand, the phase comparison between the rising timing of the output signal (c) of the AND gate (3) and the wide pulse (n) (FIG. 3) from the window pulse generation circuit (16) is performed by the second phase detection circuit (17). ). Here, the same symbols in FIGS. 2 and 3 indicate the same signals. Therefore, in the state before the time t _{1 in} FIG. 3, the selector circuit (14)
From the first internal H pulse (D) is assumed to be output, p ₁ shown wide pulse (j) is in this _state, p
₂ and it is detected whether or not the rising edge of the signal (c) exists within the pulse (p ₁ ) (p ₂ ) period. That is, when the rising edge does not exist within the period as in the p ₁ period, the output (i) of the second phase detection circuit (17) is maintained in the high level state, but as in the p ₂ period, If the rising edge exists within the period, the detection output is generated at the time point t ₁ . Then, this rise causes the output (i) of the flip-flop (15) to be inverted, which causes the selector circuit (14) to output the first internal H pulse (d) from the above-mentioned state to the second internal. The state is switched to output the H pulse (e).

Therefore, the pulse (L) given from the window pulse generation circuit (16) to the first synchronization circuit (4) also becomes the second internal H pulse (E) as shown in the figure after the time point t ₁ .
This pulse (e) synchronizes (acquires) the signal (c) as described above, and the signal (f) is obtained from the first synchronization circuit (4). That is, here, among the first and second internal H-pulses (d) and (e), the phase sufficiently separated from the leading edge (rising) position of the external V signal (c) of the frame period from the AND gate (3) is selected. That is, the other internal H pulse is selected, and the V signal (c) is synchronized by the H pulse. The wide pulse (L) from the window pulse generation circuit (16) is also switched as shown in the figure, and the above operation is repeated thereafter.

Next, the internal V signal (g) (FIG. 2) of the frame period obtained from the second synchronizing circuit (5) as described above resets the first counter (6) at its leading edge. Therefore, this first
The counter (6) counts the number of first internal H pulses from one reset period to the next reset, that is, the number of first internal H pulses in one frame period (2V), and presets the count value in the second counter (7). This second counter (7)
Is also reset at the leading edge of the signal (g), and after this reset, the 2f _H pulse from the frequency dividing circuit (10) is counted. Then, the second counter (7) generates an output when it counts up to the preset value, and again counts up to the preset value, and then is reset by the next internal V signal (g). This operation is repeated. Therefore, as the output signal of the second counter (7), the internal V of the field period synchronized with the external V signal (a) as shown in FIG.
A signal will be obtained.

Since the first synchronization circuit (4) operates at two different synchronization timings depending on the state of the flip-flop (15), in order to always obtain an internal V signal of a constant phase, 1. The output signal of the synchronization circuit (4) is synchronized again with the internal H pulse of a constant phase, but the supplied external V signal is not significantly changed in phase, that is, the above-mentioned two synchronization timings. The second synchronizing circuit (5) can be eliminated when the switching of the above does not occur frequently and the internal V signal which is not so strict is required.

The pulse supplied to the second synchronization circuit (5) and the first counter (6) is the first second internal H pulse (d).
Either one of (e) or the internal H pulse of the third phase may be used, or a pulse having an appropriate frequency division ratio may be extracted from the frequency division circuit (13) and used. .

(G) Effect of the Invention According to the vertical synchronizing signal generating circuit of the present invention, it is possible to deal with various external vertical synchronizing signals having different vertical frequencies or a phase relationship with the horizontal synchronizing signal. It is possible to create an internal vertical synchronization signal that is stable and accurate with respect to the phase fluctuation of. Moreover, the circuit configuration is relatively simple and can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining the operation thereof. (1): External vertical sync signal input terminal, (8): Internal vertical sync signal output terminal, (12): External horizontal sync signal input terminal.

Claims (1)

[Claims] 1. An oscillator for generating a signal having a horizontal synchronizing signal frequency of n times (n is an integer) synchronized with an external horizontal synchronizing signal, an internal vertical based on an oscillation signal obtained from the oscillator and an external vertical synchronizing signal. In an internal vertical synchronizing signal generating circuit including a counter for generating a synchronizing signal, reference signal generating means for generating first and second reference signals having different phases at the horizontal synchronizing signal frequency based on the oscillation signal from the oscillator, A synchronizing means for fetching an external vertical synchronizing signal with any one of the first and second reference signals, synchronizing the external vertical synchronizing signal with the reference signal, and then supplying the counter to the counter, and the first and second synchronizing signals. When it is detected that there is no phase difference by the phase comparison means for comparing the phase of the selected reference signal of the two reference signals with the external vertical synchronizing signal, the phase comparison means A vertical synchronizing signal generating circuit, comprising: means for switching a reference signal supplied to the synchronizing means.