JPH02288787A - Clock pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate a stable clock pulse by providing a PLL circuit, synchronizing circuit and a gate circuit, defining a composite synchronizing signal before the passage of gate as the input signal of the PLL circuit when the synchronizing circuit is set in an asynchronous state and defining the composite synchronizing signal after the passage of the gate as the input signal of the PLL circuit when the synchronizing circuit is set in a synchronous state. CONSTITUTION:In a select switch 3, when a horizontal synchronization compensating circuit 1 is set in the asynchronous state, the composite synchronizing signal before the passage of a gate circuit 2 is selected and when the circuit 1 is set in the synchronous state, the composite synchronizing signal after the passage of the gate circuit 2 is selected. The composite synchronizing signal selected by the select switch 3 is supplied to a phase comparator 41 of a PLL circuit 4. This comparison output is passed through an LPF 42 and used as the control voltage of a VCO 43. The oscillating clock of the VCO 43 is supplied to the horizontal synchronization compensating circuit 1. Thus, since only the composite synchronizing signal is inputted to the PLL circuit 4 at normal timing in the synchronous state by the operation of an window pulse, the circuit operation of the PLL circuit is made stable.

Description

TECHNICAL FIELD The present invention relates to a clock pulse generation circuit, and more particularly to a circuit that generates a clock pulse synchronized with a horizontal synchronization signal in a composite synchronization signal.

Background Art In order to digitally process a video signal (hereinafter referred to as a video format signal) obtained by reading and demodulating a recording medium such as a video disk or video tape, a high frequency clock pulse synchronized with the video format signal is required. It becomes necessary. For this purpose, a PLL (Phase Locked Loop) for clock pulse generation is used.
A clock pulse generation circuit configured to phase-lock the circuit to a horizontal synchronization signal in a video format signal is used. In this clock pulse generation circuit, countermeasures against disturbances caused by vertical equalization pulses in the composite synchronization signal are a problem.

Conventionally, as a countermeasure against disturbances caused by this vertical equalization pulse, the vertical equalization pulse was extracted from the composite synchronization signal through analog processing to produce only the horizontal synchronization signal, and then manually inputted to the PLL circuit. As shown in the publication, a configuration was adopted in which the operation of the phase comparator in the PLL circuit is stopped and the circuit is placed in an open state during the vertical retrace period.

However, if the vertical equalization pulse is deleted by analog processing as in the former case, the capacitor (C
) and resistor (R), the time constant needs to be adjusted. On the other hand, if the operation of the phase comparator in the PLL circuit is stopped as in the latter case, the generated lock pulse will be shifted during that time.

Summary of the Invention The present invention has been made in view of the above-mentioned points.
, R and their adjustment, and which can generate stable clock pulses without being disturbed by stationary equalization pulses.

The clock pulse generation circuit according to the present invention includes a PLL circuit that generates a clock pulse that is phase-synchronized with an input signal, and operates based on the lock pulse generated by this PLL circuit to generate a window pulse at the period of a horizontal synchronization signal. It also includes a synchronous circuit that determines the synchronous state with respect to the composite synchronous signal, and a gate circuit that allows the composite synchronous signal to pass only during the existence period of the window pulse. The configuration is such that the composite synchronization signal after passing through the gate is used as a human input signal for the PLL circuit.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1 showing an embodiment of the present invention, a composite synchronization signal is extracted by a synchronization extraction circuit (not shown) from a reproduced video format signal obtained by reading and demodulating a recording medium such as a video disk or a video tape. ,
This reproduced composite synchronization signal is supplied to a horizontal synchronization compensation circuit 1 as a synchronization circuit. This horizontal synchronization compensation circuit 1 operates using a clock pulse generated by a PLL circuit 4, which will be described later, as a system clock.
The input composite synchronization signal is sent to hunting logic circuit 1.
1 and the synchronization state detection logic circuit 12, respectively. The hunting logic circuit 11 determines whether the hunting mode is synchronization pull-in or the other non-hunting mode based on the presence or absence of input of a composite synchronization signal and the synchronization flag supplied from the synchronization state detection logic circuit 12. When a composite synchronization signal is input to the hunting logic circuit 11 in the hunting mode, the composite synchronization signal passes through the hunting logic circuit 11 and the OR gate circuit 13 and becomes the load (LOAD) input of the synchronization counter 14. By this load input, the synchronous counter 14 is loaded with the load value set by the loading logic circuit 15, and at the same time, the synchronous counter 14 starts counting at the cycle of the system clock.

Based on the count value of the synchronization counter 14, the timing generation circuit 16 generates a synchronization signal, the window generation circuit 17 generates a window pulse of a predetermined width at intervals of one horizontal scanning period ±α clock, and further detects the window end. The circuit 18 detects the window end, that is, the falling edge of the window pulse. The detection output of the window end detection circuit 18 passes through the OR gate circuit 13 and becomes a load input of the synchronous counter 14, and also becomes a trigger input of the loading logic circuit 15. The loading logic circuit 15 sets a predetermined load value in response to the detection output of the window end detection circuit 18.

The synchronous state detection logic circuit 12 includes a synchronous compensation counter 19
The synchronization compensation counter is used to determine whether or not the synchronization state is based on the count value of the synchronization compensation counter. 19 is set as count enable, and the count value N is a predetermined value (
For example, when the signal becomes "9"), the synchronization flag is set to "H" level, that is, the synchronization state is set, and then, if a composite synchronization signal is input during the existence period of the window pulse, the synchronization compensation counter 19 is cleared, and further, the synchronization state is set to the synchronization state. If the composite synchronization signal is not input during the existence period of the window pulse, the synchronization compensation counter 19 is enabled for counting, and when the count value reaches a predetermined value (for example, "4°"), it is determined that the synchronization is out of synchronization and the synchronization flag is set to " The configuration is such that a synchronization detection logic is set to the L'' level.

The composite synchronization signal also serves as a power source for each of the AND gate circuit 2 and the selection switch 3, both of which are powered by two people. AND gate circuit 2
The window pulse generated by the window generation circuit 17 is used as an external power, and the composite synchronization signal is passed only during the existence period of the window pulse. The composite synchronization signal that has passed through the AND gate circuit 2 serves as an input to the selection switch 3. The selection switch 3 is normally located on the side of the fixed contact a, and is switched to the side of the fixed contact when an "H" level synchronization flag (signal indicating that it is in the synchronized state) is supplied from the synchronization state detection logic circuit 12. That is, in the selection switch 3, when the horizontal synchronization compensation circuit 1 is in an asynchronous state, the composite synchronization signal before passing through the gate circuit 2 is selected, and when it is in a synchronization state, the composite synchronization signal after passing through the gate circuit 2 is selected. will be done.

The composite synchronization signal selected by the selection switch 3 is supplied to the phase comparator 41 of the PLL circuit 4. For example, an edge comparison type phase comparator is used as the phase comparator 41, and in this phase comparator 41, as shown in FIG. ) 43 is divided by the frequency divider 44, and the phase difference between the horizontal scanning frequency (15,734Kl(z)) and the edge (b) of the divided clock is detected, and this value is calculated as the deviation. A comparison output (C) of pulse width W according to is derived.

This comparison output! It passes through 1LPF (low pass filter) 42 and becomes the control voltage of VC043. The oscillation clock of VC043 is supplied to the horizontal synchronization compensation circuit 1 as its system clock.

In this way, by operating the horizontal synchronization compensation circuit 1 and the PLL circuit 4 in combination, only the composite synchronization signal with normal timing is input to the PLL circuit 4 in the synchronized state due to the action of the window pulse.
In addition to stabilizing the circuit operation of the L circuit, this generation circuit can also follow video format signals with time axis fluctuations, such as those obtained by playing a recording medium such as a video disk or video tape.

Next, the circuit operation of the horizontal synchronization compensation circuit 1 will be explained with reference to the timing chart of FIG.

First, when the synchronization flag is at "L" level, that is, in an asynchronous state and the composite synchronization signal 1 is not input, the hunting logic circuit 11 is in a hunting mode, and in this hunting mode, the composite synchronization signal is not input. When is input (time js), the non-hunting mode is entered. At this time, the input composite synchronization signal passes through the hunting logic circuit 11 and the OR gate circuit 13 and becomes the load input of the synchronization counter 14. As a result, the synchronous counter 14 is incremented from the load value at the cycle of the system clock at the same time as the load value set by the loading logic circuit 15 is loaded. Then, when the count value of the synchronization counter 14 reaches the target value, a window pulse is generated in the window generation circuit 17 (time t2). At this time, window pulses are generated at intervals of one horizontal scanning period ±α clock.

If the composite synchronization signal is not input during the existence period of the window pulse, the hunting logic circuit 11 enters the hunting mode again and waits for the input of the next composite synchronization signal. Then, the next composite synchronization signal is input (time t3)
, the hunting logic circuit 11 returns to the non-hunting mode.

In this non-hunting mode, when a composite synchronization signal is input during the existence period of the window pulse (time t4)
, the synchronous state detection logic circuit 12 is the synchronous compensation counter 1
9 is set to count enable state. As a result, the count value of the synchronization compensation counter 19 increases by "1", and a counting operation is performed at the cycle of the system clock. and,
When this count value N becomes, for example, N≧9 (time t5), that is, when the composite synchronization signal continues nine times or more at a predetermined interval, the synchronization state detection logic circuit 12 detects this and sets the synchronization flag. The signal is set to "H" level, and it is determined that the synchronization state is established.

Subsequently, when a composite synchronization signal is input during the existence period of the window pulse (time t6), the synchronization state detection logic circuit 1
2 clears the synchronization compensation counter 19, so that its count value becomes N-0.

In this state, even if the erroneously detected composite synchronization signal is input outside the window pulse (time t7), this composite synchronization signal is blocked by the hunting logic circuit 11 because it is outside the window pulse. The synchronization counter 14 is never loaded.

On the other hand, when the composite synchronization signal that should be input during the existence period of the window pulse is missing (time t8), the synchronization counter 14 is loaded by the detection output of the window end detection circuit 18, so the timing generation circuit 1
6, the synchronization signal is continuously generated at synchronization intervals without any loss. At this time, the synchronization counter 14
is loaded with the corrected load value, thereby correcting the pulse width of the window pulse.

Further, if the composite synchronization signal is not input during the existence period of the window pulse, the synchronization compensation counter 19 becomes count enabled, and the count value increases by "1". For example, if this state continues four times in a row, the synchronization state detection logic circuit 12 determines that synchronization has been lost and sets the synchronization flag to "L level".

When a composite synchronization signal is input during the existence period of the window pulse before the fourth consecutive pulse (time t9), the synchronization state detection logic circuit 12 clears the synchronization compensation counter 19, and the count value becomes N-0.

With the above operation, if composite sync signals are input continuously at the correct intervals, it is determined to be in sync, and unless the composite sync signals are missed several times in succession, composite sync signals that are not at the correct intervals are excluded. By performing interpolation to compensate for missing horizontal synchronizing signals, it is possible to continuously generate horizontal synchronizing signals with correct intervals.

As described in detail, the clock pulse generation circuit according to the present invention operates based on the lock pulse generated by the PLL circuit to generate window pulses at the period of the horizontal synchronization signal, and Since the configuration is such that the composite synchronization signal a is passed only during the existence period, and the composite synchronization signal before passing through the gate is supplied to the PLL circuit in the asynchronous state, and the composite synchronization signal after passing through the gate in the synchronized state is supplied to the PLL circuit, C, There is no need for H components or their adjustment, and a stable clock can be generated without being disturbed by vertical equalization pulses.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the circuit operation of the phase comparator in FIG. 1, and FIG. 3 is a waveform diagram for explaining the circuit operation of the phase comparator in FIG. 5 is a timing chart for explaining circuit operation. Explanation of symbols of main parts 1...Horizontal synchronization compensation circuit 3...Selection switch 4...PL
L circuit 12... Synchronous state detection logic circuit 14
... Synchronous counter 16 ... Timing generation circuit 17 ... Window generation circuit 19 ... Synchronous compensation counter 41 ... Phase comparator Applicant Pioneer Corporation

Claims (2)

[Claims] (1) A clock pulse generation circuit that generates clock pulses that are synchronized with the horizontal synchronization signal in the composite synchronization signal, and a PL that generates clock pulses that are phase-synchronized with the input signal.
an L circuit; a synchronization circuit that operates based on the lock pulse generated by the PLL circuit to generate a window pulse at the period of the horizontal synchronization signal and determines a synchronization state with respect to the composite synchronization signal; and the presence of the window pulse. a gate circuit that allows the composite synchronization signal to pass only during a period; when the synchronization circuit is in an asynchronous state, the composite synchronization signal is passed through the gate circuit, and when the synchronization circuit is in a synchronized state, the composite synchronization signal after passing through the gate circuit is passed through the PLL circuit; 1. A clock pulse generation circuit comprising: means for selecting an input signal. (2) The clock according to claim 1, wherein the synchronization circuit determines that the synchronization circuit is in a synchronization state when a pulse edge of the composite synchronization signal enters a predetermined number or more consecutively within the existence period of the window pulse. Pulse generation circuit.