JPH05300399A - Pll circuit - Google Patents

Abstract

PURPOSE:To allow a clock signal generating circuit employing a PLL to synchronize with an input signal quickly. CONSTITUTION:In the clock signal generator generating a clock signal synchronously with an input signal by employing a PLL circuit provided with a phase comparator 1, an LPF 2, a VCO 3 and a 1/n counter 4, a reset terminal is provided to the 1/n counter 4, a horizontal synchronizing signal after the end of equalization pulses is detected from an input composite synchronizing signal (a), a reset pulse (e) is generated based on the horizontal synchronizing signal and the reset pulse (e) is used to reset the 1/n counter 4 to allow the generating circuit to synchronize with the input composite synchronizing signal (a) quickly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock generation circuit used for digital processing of video signals,
(Phase Locked Loop) The improvement of the synchronization stability of the circuit.

[0002]

2. Description of the Related Art In digital processing of a video signal of a television receiver or the like, a system clock signal which is synchronized with the horizontal synchronizing signal and has a frequency n times, for example, 1820 times, the horizontal synchronizing frequency fH is required. An example of a conventional circuit for generating such a clock signal is shown in FIG. In the figure, the composite synchronizing signal a separated from the video signal is the phase comparator 1
The signal output from the phase comparator is converted into a control voltage corresponding to the phase difference by a low pass filter (hereinafter abbreviated as LPF) 2 and is input to a voltage controlled oscillator (hereinafter abbreviated as VCO) 3. The VCO 3 oscillates a signal having a frequency n times the horizontal synchronizing frequency fH in accordance with the voltage level of the input, and this output is used as a clock signal for digital processing of the device and is also input to the 1 / n counter 4. The 1 / n counter 4 outputs a comparison signal f which is 1 / n the frequency of the input clock signal and is compared with the composite synchronizing signal a by the phase comparator 1. That is, the phase comparator 1, the LPF
2, a PLL (PhaseL) that maintains a predetermined phase relationship between the horizontal synchronizing signal portion of the composite synchronizing signal a and the oscillation signal of the VCO 3 by the closed loop of the VCO 3 and the 1 / n counter 4.
A clock signal locked to the horizontal synchronizing signal can be obtained by configuring a ocked loop) circuit.

However, in the above circuit, the PLL operation is disturbed by the presence of the vertical synchronizing signal and the equalizing pulse included in the vertical blanking period of the composite synchronizing signal a, and this influence is exerted even after the vertical blanking period ends. The remaining problem is that it takes time to stabilize the clock signal locked to the horizontal synchronizing signal. When the input signal is the VTR reproduction signal, the horizontal synchronizing signal becomes discontinuous due to the skew that occurs when the head is switched, and as a result, a phase gap with the comparison signal f occurs and the PLL is unlocked. Therefore, there is a problem that the synchronization of the clock signal is disturbed and it takes time to stabilize again.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and promptly converts the horizontal sync signal to the disturbance of the operation of the PLL due to the vertical blanking period or skew in the VTR reproduction signal. The present invention provides a PLL circuit which is synchronized and generates a stable clock signal.

[0005]

In order to solve the above problems, the present invention is synchronized with a horizontal synchronizing signal in a PLL circuit equipped with a phase comparator, a low pass filter, a voltage controlled oscillator and a frequency dividing counter. A clock signal generation circuit for generating a clock signal, wherein the frequency division counter has a reset function, detects a horizontal synchronizing signal after completion of an equalization pulse from an input composite synchronizing signal, and resets based on the horizontal synchronizing signal. The present invention provides a PLL circuit that resets the frequency dividing counter with a pulse.

[0006]

With the above construction, the PL according to the present invention
In the L circuit, the horizontal synchronizing signal after the end of the vertical equalizing pulse is detected from the input composite synchronizing signal, the 1 / n counter is reset by the signal of the detection, and the 1 / n counter is quickly synchronized with the horizontal synchronizing signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PL according to the present invention.
FIG. 2 is a time chart showing the operation of this circuit, which is a main part block diagram showing an embodiment of the L circuit. In addition, in FIG.
The same parts as those in FIG. In FIG. 1, reference numeral 5 denotes a vertical synchronizing signal detecting section which detects a vertical synchronizing signal included in the composite synchronizing signal a and outputs a pulse b. Reference numeral 6 is a monostable multivibrator, which outputs a pulse c having a predetermined time width triggered by the rising edge of the pulse b. Reference numeral 7 is a D-FF, which outputs a pulse d for identifying the timing of the horizontal synchronizing pulse after the end of the equalizing pulse, with the pulse c as a D input and the composite synchronizing signal a as a clock input. A reset pulse generator 8 outputs a reset pulse e based on the pulse d to reset the 1 / n counter 4.

Next, the operation of the PLL circuit according to the present invention will be described with reference to FIG. FIG. 2A is a time chart of each pulse based on the vertical synchronizing signal. In the interlaced scanning television signal, when looking at the horizontal synchronizing signal with the vertical synchronizing signal as a reference, there is a difference of 1/2 horizontal period (hereinafter abbreviated as H) between the odd field and the even field. That is, the time from the beginning of the vertical sync signal to the first horizontal sync pulse after the end of the equalization pulse is 6H in the odd field and 6.5H in the even field as shown by the composite sync signal a in FIG. Is becoming Now, the time width of the output pulse c of the monostable multivibrator 6 is set to T1, and the value of T1 is 6.0H to.
It is assumed that the value is set to an intermediate value of 6.5H. Then pulse c
Is a D input and the composite synchronizing signal a is a clock input D-
The FF 7 latches the “L” level of the pulse c at the horizontal synchronizing pulse point input 6.5H or later from the rising of the vertical synchronizing signal and outputs the pulse d. That is, it falls at the second horizontal sync pulse in the odd field and at the first horizontal sync pulse in the even field. The reset pulse generator 8 generates a reset pulse e by using the falling edge of the pulse d as a trigger,
The n counter 4 is reset.

FIG. 2B shows a horizontal synchronizing signal and a comparison signal f.
It is a figure which shows the phase relationship of. First, in the steady period, the center position of the horizontal synchronizing pulse and the falling position of the comparison signal f are input to the phase comparator 1 in a phase relationship in which they substantially coincide with each other. During the unstable period, that is, in the vertical synchronizing and equalizing period of the vertical blanking period, there is no regular horizontal synchronizing pulse, so the operation of the PLL circuit becomes unstable, and the phase of the comparison signal f is changed as shown by the arrow. Fluctuations. 1 / n counter 4 based on horizontal sync pulse after equalization pulse
Is reset, the 1 / n counter 4 starts counting time, and at the point of the next horizontal synchronizing pulse after 1H has elapsed, a comparison signal f having a substantially normal phase relation is generated and the phase comparator 1 Output. Therefore, the phase fluctuation due to the vertical synchronizing signal, the equalized pulse, the skew, or the like is quickly converged, and the normal operation of the PLL circuit is started.

In the present embodiment, in order to avoid erroneous detection of the horizontal synchronizing signal, the value of the time width T1 of the pulse c is set to 6.0H.
The intermediate value of .about.6.5H is selected, and the 1 / n counter 4 is reset based on the second (odd field) horizontal synchronizing pulse after the end of the equalizing pulse, but the value of T1 is set to 5.
It may be set to an intermediate value of 5H to 6.0H and reset at the first to stabilize more quickly, or the third with more margin may be selected. Note that the present invention is not limited to the above-described embodiment, and similar effects can be realized by various circuit configurations, such as replacing the monostable multivibrator 6 with a counter. Included in the present invention.

[0011]

As described above, P according to the present invention
In the LL circuit, the horizontal sync pulse after the end of the equalization pulse is detected in the input composite sync signal, a reset pulse is generated based on the horizontal sync pulse, and the 1 / n counter is reset. Therefore, the disturbance of the synchronization of the clock signal due to the vertical synchronization signal or the equalization pulse in the vertical blanking period, or the skew generated when the head of the VTR reproduction signal is switched, is quickly converged to reduce the influence on the screen and stabilize. There is an effect that the clock signal can be obtained.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the PLL circuit according to the present invention, FIG. 2 (A) is a diagram showing a relation of each pulse based on a vertical synchronizing signal, and FIG. 2 (B) is compared with a horizontal synchronizing signal. It is a figure which shows the phase relationship of a signal.

FIG. 3 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

 1 Phase Comparator 2 LPF 3 VCO 4 1 / n Counter 5 Vertical Sync Signal Detector 6 Monostable Multivibrator 7 D-FF 8 Reset Pulse Generator

Claims (2)

[Claims] 1. A clock signal generating circuit for generating a clock signal synchronized with a horizontal synchronizing signal in a PLL circuit comprising a phase comparator, a low pass filter, a voltage controlled oscillator and a frequency dividing counter, wherein The frequency counter has a reset function, detects the horizontal sync signal after the end of the equalization pulse from the input composite sync signal, and resets the frequency division counter with a reset pulse based on the horizontal sync signal. A characteristic PLL circuit. 2. The horizontal sync signal is detected by detecting a vertical sync signal from the composite sync signal, and detecting a horizontal sync pulse after the end of the equalization pulse according to the time from the start of the vertical sync signal. The PLL circuit according to claim 1.