JP2884643B2 - Phase synchronous clock generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a clock phase-synchronized with a horizontal synchronizing signal of a video signal, and more particularly to a skew distortion (discontinuous signal) such as a VTR reproduction signal. ).

[Conventional technology]

Conventionally, as this type of phase-locked clock generator, PL
L (Phase locked loop) is used. For example, the paper "S-VHS VCR VC-DS1000", NEC Technical Report vol.41
No. 3/1988, pp. 62-69.

FIG. 5 is a block diagram showing a configuration of a conventional phase-locked clock generator using a PLL. In the figure, 11 is a horizontal sync separation circuit having a video signal as input, 12a is a phase comparison circuit having an output of the horizontal sync separation circuit 11 as a first input,
Reference numeral 13 denotes a low pass filter LPF (low pass filter) that receives the output of the phase comparison circuit 12a as an input, and 14 denotes a voltage controlled oscillator VCO (voltage controlled oscillator) that receives the output of the LPF 13 as an input.
ator) and 15a are frequency dividers having the output of the VCO 14 as an input,
The output of the frequency divider 15a is used as the second input of the phase comparison circuit 12a,
The output of VCO14 is used as the clock output.

FIG. 6 shows a waveform diagram of each part in FIG. The horizontal sync separation circuit 11 outputs a horizontal sync signal (hereinafter referred to as HS) of the input video signal.
Is output separately, and the phase comparison circuit 12a and L
The PLL composed PF13 the VCO14 and frequency divider 15a, n times HS: generating the oscillation frequency of the (n clock multiplication number) clock (hereinafter referred to as nf _H). Horizontal sync signal HS
And when the phase synchronization of the clock nf _H is taken, the HS and nf _H
The output f _H of the phase of the frequency divider 15a which is obtained by 1 / n frequency division are also synchronized, the output of the phase comparator circuit 12a becomes constant, the oscillation of the VCO14 is stabilized.

In the FIG. 6 as the phase comparator circuit 12a, a f _N is converted into a sawtooth wave by a primary LPF, while HS is high, there is shown a case of using a method for outputting the sawtooth wave. Further, in this case, the VCO 14 used has a higher oscillation frequency as the input voltage is lower, and the LPF 13 is a phase comparator 5
The output of 2 is smoothed. The phase synchronization between HS and nf _H is shifted,
If HS is faster than f _H, so outputs the low portion of the phase comparator circuit sawtooth voltage at 12a decreases the output voltage of the LPF13 is, to increase the oscillation frequency of the VCO 14, HS and nf _H phase locked Give feedback as if to do. HS is the case of slower than f _H, it is the reverse operation.

By the way, since the reproduction signal of the VTR such as the VHS format switches signals from a plurality of reproduction heads, a discontinuous point of the signal (generally, skew distortion) occurs when the head is switched.

For example, as shown in FIG. 7, when the reproduction signal of the head (2) is delayed with respect to the reproduction signal of the head (1), the interval of HS when the head is switched from the head (1) to the head (2). Becomes longer only by the line at the time of head switching. Thereafter, the distance HS returns to the original, it is determined that the phase comparator 12a in HS later than f _H for the phase of HS and f _H is shifted to lower the oscillation frequency of the VCO 14, HS and f _H is Feedback will be applied so that the phases are synchronized. It usually takes a period of more than ten lines to return to this phase synchronization state.

[Problems to be solved by the invention]

The above-described conventional phase-locked clock generator uses a PLL. However, since the frequency divider is operated with a fixed phase, if the phase synchronization is shifted due to skew distortion, it is necessary to return to the original phase-locked state. There is a drawback in that a period of more than ten lines is required, and during that time, an out-of-sync screen is reproduced on the monitor.

An object of the present invention is to solve this problem, the skew detecting means and the frequency dividing phase control means, by changing the frequency division phase of the divider to detect the skew distortion, phase shift of HS and f _H To provide a phase-locked clock generation device capable of rapidly correcting the phase-locked clock.

[Means for solving the problem]

The configuration of the present invention comprises a horizontal sync separation circuit for inputting a video signal and separating and outputting a horizontal sync signal, and a phase comparison circuit for inputting a horizontal sync signal output and a frequency-divided output of the horizontal sync separation circuit and comparing the phases. And a low-pass filter that receives an output of the phase comparison circuit and outputs a low-frequency component thereof,
A voltage-controlled oscillator that receives the output of the low-pass filter as an input, and a frequency divider that receives the output of the voltage-controlled oscillator and outputs the frequency-divided output; A skew detector for receiving an output of the horizontal sync separation circuit and outputting a skew detection signal when the horizontal sync signal deviates from a predetermined timing range; and a dividing phase added to the frequency divider. Frequency divider control means for controlling the skew detection signal as the control input of the frequency-divided phase control means and the phase comparison circuit, and the frequency divider includes a counter and an output of the counter. A data latch group as an input, and an output of the data latch group as a data input of the counter, and using the load input of the counter as the frequency dividing phase control means. The features.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a phase-locked clock generation device according to the present invention. In the figure, 11 is a horizontal sync separation circuit that receives a video signal as an input, 12 is a phase comparator that uses the output of the horizontal sync separator 11 as a first input, 13 is an LPF that receives the output of the phase comparator 12 as an input, Reference numeral 14 denotes a VCO that receives the output of the LPF 13 as an input. Reference numeral 15 denotes a frequency divider that receives the output of the VCO 14. The output of the frequency divider 15 is used as the second input of the phase comparison circuit 12, and the output of the VCO 14 is clocked. Output. Further, the output of the horizontal sync separation circuit 11 is input to the skew detector 16, and the output of the skew detector 16 is used as the frequency division phase control input of the frequency divider 15 and the control input of the phase comparison circuit 12.

Here, the phase comparison circuit 12, the LPF 13, the VCO 14, the frequency divider
The PLL constituted by 15 performs the same operation as in FIG.

The skew detector 16 includes, for example, means for detecting the leading edge of the HS, a counter, and a comparator, and detects the leading edge of the HS as shown in FIG.
The period between one HS detection signal and the next HS detection signal is counted. Here, if the phase synchronization clock generating a 910f _H, if the counter value is the HS detected when non 906~914 (910 ± 4), operates to output a skew detection signal.

Frequency divider 15 counts up from 0 to 909 at 910 cycle nf _H clock is constructed using a counter, the counter value 227
Between f _H of ～682 a low level, in other cases, a high level. Further, a counter reset means is provided as the frequency division phase control means.

The phase comparator circuit 12 has a means for stopping the phase comparison by the control input, and if the phase synchronization of HS and f _H is established, the frequency divider to match the leading edge timing of the HS
It is necessary to adjust the whole system so that the counter value of 15 becomes 0.

In this case, if there is a skew distortion in the video input, it detects it in skew detector 16, to output a skew detection signal, the frequency divider 15 as shown in Figure 3 is reset, the f _H The phase returns to the original state. That is, the leading edge of the HS coincides with the timing at which the value of the counter of the frequency divider 16 becomes 0. Since the operation of the phase comparison circuit 12 is stopped at this time, the influence on the PLL is reduced, and the generation of the phase-synchronized clock can be stabilized.

FIG. 4 is a block diagram showing a configuration example of the frequency divider 15 of FIG. In the figure, 41 is a counter to the clock input of nf _H, 42 is f _H · reset generator which receives the output of the counter 41, the f _H output f _H · reset generator 42 frequency divider 15
and f _H output, the reset output reset input of the counter 41, 43 is a data latch group to be HS detection signal a clock input the output of the counter 41 and data input, data of the counter 41 the output of the data latch group 43 The skew detection signal is used as a control input of the data latch group 43 and a load input of the counter 41.

In this circuit, the counter 41 counts up from 0 to 909 to nf _H at 910 cycles, the f _H · reset generating circuit 42, for example, the counter value is set to low level between f _H of 227-682, a high at other times Level. And the counter value is 910
Reset signal is output at the timing
Reset.

On the other hand, the data latch group 43 latches the output of the counter 41 at the timing when the HS detection signal is output when the skew detection signal is not output, and does not latch when the skew detection signal is output. When the skew detection signal is output, the output of the data latch group 43 is
Load data to 41.

To hold the counter value of the frequency divider 15 when this way has taken the phase synchronization HS and f _H to the data latch group 43, similarly to FIG. 1, when there is a skew distortion in the video input Since the internal state of the frequency divider 15 immediately returns to the original state, the generation of the phase-locked clock can be stabilized.

In addition, in the case of FIG. 4, adjusting the counter value of the frequency divider 15 to match the leading edge timing of the HS when the phase synchronization of the HS and f _H was required in Figure 1 is taken to 0 There is an advantage that it becomes unnecessary.

〔The invention's effect〕

The present invention described above, and a skew detector and division phase control means detects a skew distortion, possible to reduce the phase shift of HS and f _H by changing the frequency division phase of the frequency divider As a result, the effect of skew distortion on the PLL can be reduced, the generation of the phase-synchronized clock can be stabilized, and the shift in the synchronization of the screen reproduced on the monitor can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a phase-locked clock generator according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the skew detector of FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the frequency divider shown in FIG. 1, FIG. 5 is a block diagram showing an example of a conventional phase-locked clock generator, and FIG. FIG. 7 is a waveform diagram of each part of the video signal, and FIG. 7 is a waveform diagram of each part of the video signal including the skew distortion of FIG. 10 ... Input terminal, 11 ... Horizontal sync separation circuit, 12,12a ...
Phase comparing circuit, 13 ...... LPF, 14 ...... VCO, 15, 15a ...... divider, 16 ...... skew detector, 20 ...... output terminal, 41 ...... counter, 42 ...... f _H reset generator, 43 Data latch group.

Claims (1)

(57) [Claims] A horizontal synchronizing separation circuit for inputting a video signal and separating and outputting a horizontal synchronizing signal; a phase comparing circuit for inputting a horizontal synchronizing signal output and a frequency-divided output of the horizontal synchronizing separation circuit and performing phase comparison; A low-pass filter that receives an output of the phase comparison circuit and outputs a low-frequency component thereof; a voltage-controlled oscillator that receives an output of the low-pass filter; A phase-synchronized clock generator that outputs the output of the voltage-controlled oscillator and outputs the clock of the horizontal sync separator when the horizontal sync signal deviates from a predetermined timing range. A skew detector that outputs a skew detection signal; and frequency-divided phase control means that controls a frequency-divided phase added to the frequency divider. The frequency divider serves as a control input to the divided phase control means and the phase comparison circuit, and the frequency divider includes a counter, a data latch group to which the output of the counter is input, and an output of the data latch group to the data of the counter. A phase-locked clock generator, wherein a load input of the counter is used as the input as the divided phase control means.