JPH0523018Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] This invention is installed in video equipment such as television receivers and image display devices, and is used to detect horizontal synchronization signals of composite video signals obtained by external input or reception. This invention relates to a horizontal synchronization circuit that inputs the signal to a PLL circuit for synchronous AFC, generates and outputs an internal horizontal synchronization signal used in horizontal deflection circuits, etc.

[Conventional technology]

Conventionally, a television receiver, which is an example of this type of video equipment, has a system that controls the operation of an internal horizontal deflection circuit, etc., to receive an externally input composite video signal such as a playback signal from a video tape recorder, or to receive an internal tuner. In order to synchronize with the horizontal synchronization signal of the composite video signal obtained as a result, that is, the composite video signal to be played on the screen, a synchronous AFC (automatic frequency control)
A horizontal synchronization circuit using a PLL circuit is provided.

The horizontal synchronization circuit controls the oscillation frequency of a voltage controlled oscillator (hereinafter referred to as VCO) in the PLL circuit based on the horizontal synchronization signal separated and extracted from the composite video signal, that is, the input horizontal synchronization signal, and An internal horizontal synchronization signal synchronized with the synchronization signal is generated, and the internal horizontal synchronization signal is output to a subsequent circuit such as a horizontal deflection circuit.

By the way, due to poor playback or poor reception of the video tape recorder, which is an external device, the composite video signal may be mixed with a video signal during the synchronization signal period, and this phenomenon is usually caused by video in sync. (VIDEO IN SYNC).

Then, it becomes video in sync,
When a video signal is mixed into the input horizontal synchronization signal, the horizontal synchronization circuit malfunctions, causing disturbances in the playback screen.

Therefore, the conventional horizontal synchronization circuit has a gate width slightly smaller than the pulse width of the horizontal synchronization signal in the previous stage of the PLL circuit, as described in Japanese Patent Application Laid-open No. 57-52268 (H04N5/06). The gate circuit is equipped with a gate circuit set to a wide and constant specified pulse width, and when the low level pulse signal shown in FIG. 4a is inputted as an input horizontal synchronizing signal by the gate circuit, Based on the gate pulse with pulse width τa, as shown in c in the same figure,
Only a signal with a period of specified pulse width τa is supplied to the PLL circuit as an input horizontal synchronizing signal to prevent the incoming video signal from being erroneously input to the PLL circuit during the video-in-sync state.

Note that the gate pulse in FIG. 4b is the same as that of the VCO
It is output at a timing synchronized with the internal horizontal synchronizing signal, and its pulse width τa is a specified pulse width τa that does not exceed the front porch and back porch in all horizontal scanning lines.
Fixed.

[Problem that the invention attempts to solve]

By the way, for example, based on playback tracking deviation of a video tape recorder, which is an external device, during the vertical retrace period of an externally input composite video signal, the first horizontal scanning period (hereinafter the horizontal scanning line period will be referred to as H) may occur. Phase distortion (skew distortion) of the synchronization signal may occur during the period on the leading edge side of about H to 10th H.

Note that, due to deterioration of the reception condition, phase distortion of the synchronizing signal may occur in the composite video signal obtained by reception during the vertical retrace period.

When phase distortion occurs, the position (interval) of the horizontal synchronization signal in the composite video signal deviates from its normal position depending on the degree of distortion.

Therefore, as mentioned above, in the conventional horizontal synchronization circuit in which the gate circuit is operated by a gate pulse with a specified pulse width τa, separation and extraction are performed based on phase distortion, as is clear from, for example, FIGS. While the phase of the input horizontal synchronization signal is disturbed, the input horizontal synchronization signal cannot be extracted, and an internal horizontal synchronization signal is generated and output asynchronously to the input horizontal synchronization signal.

Furthermore, even if the synchronization signal of the composite video signal returns to normal, it takes time for the internal horizontal synchronization signal to synchronize with the input horizontal synchronization signal, depending on the response speed of the PLL circuit.

Therefore, in conventional horizontal synchronization circuits, when phase distortion occurs in the synchronization signal during the vertical blanking period of a composite video signal, the internal horizontal synchronization signal is disturbed, for example in the case of television receivers and image display devices. There is a problem that the playback screen may be distorted, and good screen playback cannot be performed.

This invention was made with the above points in mind.

[Means for solving problems]

Means for solving the above problems will be explained below with reference to FIG. 1, which corresponds to an embodiment.

This invention is provided in video equipment such as television receivers and image display devices, and gate-processes an input horizontal synchronizing signal separated from a composite video signal and inputs it to a PLL circuit 1 for synchronous AFC.
The PLL circuit 1 controls the oscillation frequency of the voltage controlled oscillator, that is, VCO 2, based on the input horizontal synchronization signal, and divides the frequency of the oscillation signal of the VCO 2 to generate an internal horizontal synchronization signal synchronized with the input horizontal synchronization signal. A horizontal synchronization circuit that outputs an oscillation signal includes: a gate circuit 3 for eliminating unnecessary signals, which is provided before the PLL circuit 1 and whose signal passing period is varied in proportion to the pulse width of the gate pulse; The pulse width of at least a portion of the leading edge side of the vertical retrace period is varied to be wider than a specified pulse width for horizontal synchronization signal extraction, based on the frequency signal and a signal synchronized with the vertical synchronization signal of the composite video signal. A technical measure is taken to include a gate pulse generation circuit 4 that forms and outputs the gate pulse.

[Effect]

Therefore, according to this invention, in the vertical blanking period of the composite video signal, the width of the gate pulse supplied to the gate circuit 3 is equal to the specified pulse at least during a part of the period on the leading edge side where phase distortion of the synchronizing signal occurs. Even if the input horizontal synchronizing signal is varied to be wider than the width and the position of the input horizontal synchronizing signal is shifted due to phase distortion, the input horizontal synchronizing signal is extracted by the gate circuit 3.

Furthermore, during periods other than the above-mentioned part of the period, a gate pulse having a specified pulse width is supplied to the gate circuit 3, thereby preventing erroneous extraction due to video-in-sync.

Therefore, even when phase distortion occurs in the synchronization signal of the composite video signal, the input horizontal synchronization signal is input to PLL circuit 1 without being affected by video signal mixing due to video in sync, and the internal horizontal A synchronization signal is stably generated and output in synchronization with an input horizontal synchronization signal, and good screen reproduction of television receivers and image display devices can be performed, thereby solving technical problems.

〔Example〕

Next, this invention will be explained in detail with reference to FIGS. 1 to 3 showing one embodiment thereof.

Figure 1 shows the case where it is installed in a television receiver, and in the figure, 1 is a PLL for synchronous AFC.
The circuit consists of a phase comparator 5, a low-pass filter 6, a VCO 2, and a frequency divider 7. 3 is
This is a gate circuit for eliminating unnecessary signals provided before the PLL circuit 1, and the signal passing period is varied in proportion to the pulse width of the gate pulse output from the gate pulse generation circuit 4.

Then, the horizontal synchronization signal of the composite video signal consisting of the playback signal of the video tape recorder, which is an external device, or the reception signal of the internal tube is separated and extracted by a synchronization separation circuit (not shown), and the input horizontal synchronization signal hi The signal is input to the gate circuit 3 as a signal.

Furthermore, the phase of the input horizontal synchronizing signal hi passed through the gate circuit 3 is compared with the internal horizontal synchronizing signal ho generated and output from the frequency divider 7 by the phase comparator 5 of the PLL circuit 1 .

By the way, the phase comparator 5 receives the input horizontal synchronization signal
Using hi as a reference signal, a signal with a phase difference between both horizontal synchronizing signals hi and ho is formed.

Then, the phase difference signal from the phase comparator 5 is converted into a voltage signal by the low-pass filter 6, and the voltage signal is supplied to the VCO 2 as a control voltage for the oscillation frequency.

At this time, the free-running oscillation frequency of the VCO 2 is set to N times the frequency f _H of the horizontal synchronizing signal, and the oscillation frequency is controlled in proportion to the voltage signal of the low-pass filter 6 .

Further, the oscillation signal of VCO2 is input to the frequency divider 7, and the oscillation signal of VCO2 is input to the frequency divider 7.
The frequency is divided, and the generated horizontal synchronization signal, that is, the internal horizontal synchronization signal ho synchronized with the input horizontal synchronization signal hi, is output from the frequency divider 7 to the subsequent stage circuit and the phase comparator 5.

Incidentally, the frequency divider 7 is composed of, for example, an N-stage flip-flop, and outputs a frequency-divided signal of each stage including the internal horizontal synchronizing signal ho to the generating circuit 4.

Meanwhile, in the receiver, based on the vertical synchronization signal of the composite video signal output from the synchronization separation circuit, a vertical deflection circuit of the receiver, for example,
As shown in Figure a, the period from the leading edge of the 1st H to the trailing edge of the 21st H in the vertical blanking period of each field of the composite video signal, that is, the vertical blanking period Tv
The internal vertical synchronization signal v becomes high level only when
It is formed using a PLL circuit or CR integrator.

Then, the internal vertical synchronization signal v is input to the generation circuit 4 as a signal synchronized with the vertical synchronization signal of the composite video signal, and the generation circuit 4 generates a signal based on the frequency division signal of the frequency divider 7 and the vertical synchronization signal v. A gate pulse is formed and output to the gate circuit 3 as described below.

That is, the generation circuit 4 processes the frequency-divided signal of the frequency divider 7 with a logic gate circuit internally, and generates a pulse with the conventional prescribed pulse width τa and a pulse with a pulse width τb wider than the prescribed pulse width τa. The central position of the internal horizontal synchronizing signal ho is formed as the pulse intermediate position, and based on the vertical synchronizing signal v, as shown in FIG. A pulse with a pulse width τb is output as a gate pulse during the vertical retrace period Tv.

Furthermore, the gate circuit 3 consists of an analog switch that is turned on only during the period τa or τb of the input gate pulse, and the signal passing period is varied to τa and τb by the gate pulse, and each 1H
Only the signal input during the signal passing period τa or τb is supplied to the phase comparator 5 as a regular input horizontal synchronizing signal hi.

Then, during the period excluding the vertical retrace period Tv, the gate circuit 3 is turned on only for a period with a pulse width τa slightly wider than the pulse width of the input horizontal synchronizing signal.
Only the input horizontal synchronizing signal hi is supplied to the PLL circuit 1, eliminating the influence of video in sync, and during the vertical retrace period Tv, the on period of the gate circuit 3 becomes a wide period τb based on the gate pulse. Therefore, phase distortion occurs in the synchronization signal of the composite video signal due to playback tracking deviation of the video tape recorder, etc., and the position of the input horizontal synchronization signal hi changes during the vertical retrace period Tv as shown in Figure 3a. Even if the input horizontal synchronizing signal hi varies, the input horizontal synchronizing signal hi is extracted and supplied to the PLL circuit 1 by turning on the gate circuit 3 during the period of pulse width τb shown in FIG.

Therefore, not only the effects of video-in-sync but also the effects of phase distortion of the synchronization signal during the vertical blanking period Tv are eliminated to ensure that the input horizontal synchronization signal hi is
At this time, even if the input horizontal synchronizing signal hi changes due to the presence or absence of phase distortion, the VCO 2 follows it more quickly than before, so the internal horizontal synchronizing signal ho Stably generated in synchronization with signal hi.

Therefore, television receivers have a high S/N
, screen playback can be performed without being affected by phase distortion of the video in sync and horizontal synchronization signals, and at this time, it is possible to perform stable and good screen playback, especially since the conventional screen disturbances caused by phase distortion are prevented. Ru.

Note that the period of the pulse width τb mentioned above is arbitrarily set based on experiments and the like.

Further, in the embodiment, during the vertical retrace period Tv,
The pulse width of the gate pulse was set to a wide τb, but
Since phase distortion of the synchronization signal is particularly likely to occur on the leading edge side of the vertical retrace period Tv, even if the pulse width of the gate pulse is changed to a wider τb for a part of the period on the leading edge side of the vertical retrace period Tv, it is not possible to carry out the implementation. The same effect as in the example can be obtained.

In the above embodiment, the present invention is applied to a horizontal synchronizing circuit of a television receiver, but it is of course applicable to horizontal synchronizing circuits of various video equipment such as an image display device.

[Effect of idea]

As described above, according to the horizontal synchronization circuit of this invention, the signal passing period of the gate circuit provided at the front stage of the PLL circuit for synchronous AFC is changed to the video input at least on the leading edge side of the vertical retrace period of the composite video signal. - By eliminating the influence of the sink and making the period wider than the period for extracting the input horizontal synchronization signal, it is possible to reliably extract the input horizontal synchronization signal with phase distortion during the vertical retrace period and supply it to the PLL circuit. ,video·
The input horizontal synchronization signal is supplied to the PLL circuit while eliminating the effects of in-sync and phase distortion, and the internal horizontal synchronization signal is stably generated in synchronization with the input horizontal synchronization signal, such as television receivers and image display devices. It is possible to improve the screen playback characteristics of.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the horizontal synchronization circuit of this invention, FIG. 1 is a block diagram, FIGS. 2a and 2b are timing charts for explaining the operation of the gate pulse generation circuit, and FIG. 4a to 4c are timing charts for explaining the operation of the gate circuit during the vertical retrace period, and FIGS. 4a to 4c are timing charts for explaining the operation of the conventional horizontal synchronizing circuit. 1...PLL circuit, 2...VCO, 3...gate circuit, 4...gate pulse generation circuit, 7...frequency divider.

Claims (1)

[Scope of claim for utility model registration] Synchronization is provided in video equipment such as television receivers and image display devices, and is synchronized by gate processing the input horizontal synchronization signal separated from the composite video signal.
Input to the PLL circuit for AFC, and by the PLL circuit,
a horizontal synchronization circuit that controls the oscillation frequency of the voltage controlled oscillator based on the input horizontal synchronization signal, divides the frequency of the oscillation signal of the oscillator, and generates and outputs an internal horizontal synchronization signal synchronized with the input horizontal synchronization signal; , a gate circuit for eliminating unnecessary signals, which is provided before the PLL circuit and whose signal passing period is varied in proportion to the pulse width of the gate pulse; Based on a signal synchronized with a synchronization signal, the gate pulse is formed and outputted, and the pulse width of at least a part of the leading edge side of the vertical retrace period is varied to be wider than a specified pulse width for horizontal synchronization signal extraction. A horizontal synchronization circuit equipped with a gate pulse generation circuit.