JP2591819B2 - Character signal synchronous playback circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV character signal reproducing circuit, and in particular, to a character signal synchronization circuit for outputting a display clock capable of obtaining a stable reproduction screen regardless of the presence or absence of an input character signal. It relates to a reproduction circuit.

[Conventional technology]

In TV teletext broadcasting, text and graphic information is digitized and transmitted while being superimposed on the vertical retrace period of the composite video signal. In reproducing the character signal, the superimposed character signal is extracted from the vertical retrace period of the transmitted composite video signal, and various timing pulses necessary for reproduction are reproduced based on the simultaneously transmitted reference signal. Must. The character signal extracted here and the reproduced various timing pulses are input to a decoder, where they are subjected to digital signal processing, then D / A converted, output as RGB signals, and displayed on a screen.

FIG. 5 shows a block diagram of a conventional general character signal synchronous reproducing circuit for reproducing a clock necessary for reproducing a character signal. In FIG. 5, the composite video signal on which the character signal input to the input terminal 1 is superimposed is input to the sync separation circuit 3 and to the clock gate circuit 11. The synchronization separation circuit 3 separates a horizontal synchronization signal from the input composite video signal and inputs the same to one input terminal of the phase detection circuits 1 and 4. The VCO 5 oscillates at a free-run frequency (approximately 5.73 MHz) that is 364 times the horizontal synchronization signal. One is output to the display clock output terminal 9 as a display clock, and the other is divided by 1/364. Input to the circuit 6. In the 1/364 frequency dividing circuit 6, the oscillation carrier from the VCO 5 is frequency-divided by 1/364 and then inputted to the other input terminal of the phase detecting circuit 1. Here, the phase detectors 1, 4, VCO5, and the 1/364 frequency divider 6 constitute a PLL circuit 7, which detects the phase difference between the horizontal synchronizing signal and the carrier from the 1/364 frequency divider. Outputs the corresponding DC control voltage, thereby controlling the oscillation frequency of VCO5,
It is always output from the display clock output terminal 9 as a display clock synchronized with the input horizontal synchronization signal. This display clock is used as a display timing clock when a character signal is displayed on a screen.

The clock gate circuit 11 gates and extracts a clock run-in signal (CR signal) transmitted as a reference signal from the superimposed character multiplexed signal, and extracts the phase.
Input to one input terminal of 2,12. The oscillation circuit 10 is a 5.73 MHz reference clock oscillation circuit using a crystal oscillator or the like, and supplies a clock to the other input terminals of the phase detection circuits 2 and 12 and the phase shift circuit 13. The phase detection circuits 2 and 12 detect a phase difference between the CR signal and the clock, output a DC control voltage corresponding to the phase difference, and apply the DC control voltage to the phase shift circuit. In the phase shift circuit, the phase of the clock from the oscillation circuit 10 is controlled by the DC control voltage from the phase detection circuit 2 so that the phase is adjusted with the CR signal, and the data clock is output from the data clock output terminal 15 as a data clock. This data clock is used as a timing clock when sampling the sent character signal digital data signal.

[Problems to be solved by the invention]

In the conventional character signal synchronous reproduction circuit described above, in the state of no input signal, the phase detection circuit does not operate, so that the VCO is in a free-run state, and a clock of the VCO free-run frequency is used as a display clock. Is output, and the variation in the free-run frequency appears as it is. There are several modes for reproducing a character signal on the screen, including superimpose, superimposing subtitles, and displaying all characters on a TV screen by superimposing the character signal. When displaying these character signals, normally, sent character signal data is stored once in a memory and then read out, and then displayed. In particular, full-screen character display is required even when there is no input signal. In this case, a stable display clock is required in order to display a stable screen even in this state. However, in the above-described conventional character signal synchronous reproduction circuit, when the signal changes from a signaled state to a non-signaled state, the display clock frequency shifts and the screen display flows.
There are problems such as instability. As a means to solve this problem, it is possible to suppress the frequency variable range of the VCO and suppress the variation of the free-run frequency.
There is a problem in that the pull-in range of O cannot be taken and it is not possible to cope with the frequency fluctuation of the input and composite video signals. Further, as a solution, a separately stable reference oscillation circuit can be provided outside, and this oscillation clock and the clock from the VCO can be switched between when there is a signal and when there is no signal, but the number of parts increases. There are problems such as an increase in the number of terminals when integrated.

[Means for solving the problem]

A character signal synchronous reproduction circuit according to the present invention includes: a composite video signal on which a character multiplexed signal is superimposed; a synchronizing separation circuit for separating a horizontal synchronizing signal from the composite video signal; and a first clock based on the horizontal synchronizing signal. , A clock gate circuit for extracting a clock run-in signal from a character multiplexed signal in a composite video signal, an oscillation circuit for generating a second clock as a reference clock, and a clock run-in for the second clock. A data clock recovery circuit for generating a data clock having a phase equal to the phase of the signal; and an input signal detection circuit for detecting the presence or absence of input of the composite video signal, wherein the first clock and the second clock are connected to the input signal detection circuit. It is characterized in that it is switched by an output and output as a display clock. According to a preferred aspect of the present invention, the PLL circuit includes a phase detection circuit that detects a phase of the horizontal synchronization signal and the frequency-divided signal, a voltage-controlled oscillator whose oscillation frequency is controlled by an output of the phase detection circuit, and A frequency dividing circuit for dividing the output of the voltage controlled oscillator to output the above-mentioned divided signal. The input signal detecting circuit determines the synchronization between the horizontal synchronizing signal and the divided signal and outputs a composite video signal. Detects the presence or absence of input. According to still another aspect, the input signal detection circuit counts the second clock generated during the horizontal synchronization signal, generates a determination result signal indicating whether or not a composite video signal has been input, and combines the signal with a composite signal. It is output outside the period of the vertical synchronizing signal of the video signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 5, the same functional elements and the same functional blocks as those in the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In FIG. 1, a composite video signal input to an input terminal 1 is input to a sync separation circuit 3 and a clock gate circuit 11. The sync separation circuit 3 separates a horizontal sync signal component from the input composite video signal, and inputs the separated components to the input signal detection circuit 2 and the phase detection circuits 1 and 4. The phase detectors 1, 4, VCO5, and the 1/364 frequency divider 6 constitute a PLL circuit 7, and the VCO 5 synchronizes with the horizontal synchronizing signal of the input composite video signal, and the frequency is 364.
The double clock 1 is output and supplied to one input terminal of the switching circuit 8. The oscillation circuit 10 is supplied to the other input terminal of the data clock reproduction circuit 14 and the switching circuit 8 as a clock 2 which is stabilized by using a crystal oscillator or the like. The input signal detection circuit 2 detects the presence or absence of an input signal by performing synchronization determination between the horizontal synchronization signal from the synchronization separation circuit 3 and the carrier from the 1/364 frequency divider 6, and outputs a control signal in accordance with the input signal. I do.

In the switching circuit 8, when there is an input signal according to the control signal from the input signal detection circuit 2, the clock 1 from the VCO 5 is output.
When there is no input signal, the clock 2 from the oscillation circuit 10
Is output from the display clock output terminal 9 as a display clock.

FIG. 2 is a circuit diagram showing an embodiment of the input signal detection circuit 2. In FIG. 2, a positive polarity horizontal synchronizing signal is input from a synchronizing separation circuit 3 from a terminal 16 to the bases of transistors Q ₄ and Q ₆ . The base of the transistor Q ₁ included in the transistor Q ₂ and the differential circuit has positive polarity carriers from 1/364 frequency divider circuit 6 is inputted. Horizontal sync signal and 1/364
Assuming that the carrier from the frequency dividing circuit 6 is synchronized, the transistors Q ₆ and Q ₇ become active at the timing of the horizontal synchronizing signal, and a current flows from the power supply terminal 19 to the resistor R ₈ , the transistors Q ₆ and Q ₇ , and the transistor Q _{6 3} becomes active. At this time, since the transistor Q ₅ is a cut-off state, the transistor Q ₄ also becomes cut off, the transistor Q ₃ from the power source terminal 19 to the capacitor C, current is supplied through the resistor R _6, is charged,
The base potential of the transistor Q ₈ becomes high. Then the synchronization of the carrier from the horizontal synchronizing signal and a 1/364 frequency dividing circuit 6, the outside, the transistors Q ₄ and Q ₅ are generated timing to be active at the same time, this time the transistor Q ₃ are the cut off Therefore, the electric charge charged in the capacitor C is
R ₇ , discharged through transistors Q ₄ and Q ₅ ,
The base potential of the transistor Q ₈ will be low. Terminal 16
The state in which the horizontal synchronizing signal is not input, that is, when no signal, the transistor Q _6, it is not serving as an active state, therefore since the capacitor C is not charged, the base potential of the transistor Q ₈ becomes抵位. The transistors Q ₈ , Q ₉ ,
The resistors R ₉ , R ₁₀ , R ₁₁ , R _{12 form} a comparison circuit, and the resistors R ₁₁ , R ₁₁
By comparing the reference potential determined at ₁₂ with the charged potential of the capacitor C, the presence or absence of an input signal is determined and the output terminal 18 is determined.
And outputs a control signal for controlling the switching circuit 8.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In FIG. 1, the same functional elements and the same functional blocks as those in the first embodiment of the present invention are denoted by the same reference numerals, and detailed description is omitted.

3, a composite video signal input to the input terminal 1 is input to a terminal 20 of the input signal detection circuit 23, a horizontal synchronization signal is input to a terminal 21 from the synchronization separation circuit 3,
The clock from the oscillation circuit 10 is input to 22. Terminal
From 18, the presence or absence of an input signal is detected, and a control signal is output in accordance with the detection. Next, FIG. 4 is a block diagram showing the configuration of the input signal detection circuit 23, and the operation will be described.

In FIG. 4, the composite video signal input to the terminal 20 is input to the vertical sync separation circuit 24. The vertical synchronization separation circuit 24 separates the vertical synchronization signal from the composite video signal and supplies the signal to the terminal G of the latch circuit 26. In the counter circuit 25,
The horizontal synchronization signal from the synchronization separation circuit 3 is input from a terminal 21 and the clock from the oscillation circuit 10 is input from a terminal 22. The input clock for one cycle period of the input horizontal synchronization signal is Counting is performed, and if the count number result is within a certain range, it is determined that an input signal is present, and a determination result signal is supplied to the terminal D of the latch circuit 26. In the latch circuit 26, during the vertical synchronization period, the frequency of the output horizontal synchronization signal of the synchronization separation circuit 3 is shifted. Therefore, the latch is performed based on the presence or absence of an input signal during the period other than the vertical synchronization signal period. Output more. With this control signal, the clock 1 from the VCO 5 and the clock 2 from the oscillation circuit 10 are switched according to the presence or absence of an input signal and output from the display clock terminal 9 as a display clock, as in the first embodiment. .

〔The invention's effect〕

As described above, the present invention provides an input signal detection circuit, and switches and outputs and supplies a clock signal from a VCO and a clock signal from an internal reference oscillation circuit depending on the presence or absence of an input signal as a display clock. There is an effect that a stable display clock can always be supplied regardless of the presence or absence of an input signal, and a stable teletext screen can be obtained. Further, since the reference oscillation circuit is also used for the data clock recovery circuit, the circuit scale can be reduced and the number of external parts can be reduced. Further, in the case of an integrated circuit, one terminal can be used as a display clock output terminal, and the number of terminals can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram of an input signal detection circuit of FIG. 1, and FIG. 3 is a block showing another embodiment. FIG. 4 is a circuit diagram of the input signal detection circuit of FIG. 3, and FIG. 5 is a block diagram of a conventional example. 1 ... input terminal, 2, 23 ... input signal detection circuit, 3 ... synchronization separation circuit, 4 ... phase detection circuit 1, 5 ... VCO, 6 ...
... 1/364 frequency dividing circuit, 7 ... PLL circuit, 8 ... Switching circuit, 9 ... Display clock output terminal, 10 ... Oscillator circuit, 11
…… Clock gate circuit, 12 …… Phase detection circuit 2, 13…
... Phase shift circuit, 14 ... Data clock recovery circuit, 15
…… Data clock output terminals, R _{1 to} R ₁₂ …… Resistors, C…
... capacitor, Q ₁ ~Q ₉ ...... transistor.

Continuation of front page (72) Inventor Hideki Teramatsu 3-5-24 Miyahara, Yodogawa-ku, Osaka-shi, Osaka NEC Home Electronics Co., Ltd. (56) References JP-A-62-186684

Claims (3)

(57) [Claims] 1. A composite video signal on which a character multiplexed signal is superimposed is inputted, and a synchronizing separation circuit for separating a horizontal synchronizing signal from the composite video signal, and a PLL for generating a first clock based on the horizontal synchronizing signal. A clock gate circuit for extracting a clock run-in signal from the character multiplexed signal in the composite video signal; an oscillation circuit for generating a second clock that is a reference clock; A data clock recovery circuit for generating a data clock having a phase equal to the signal phase; and an input signal detection circuit for detecting the presence or absence of the input of the composite video signal. A character signal synchronous reproduction circuit characterized in that the character signal synchronous reproduction circuit is switched by the output of a signal detection circuit and output as a display clock. 2. The phase-locked loop (PLL) circuit detects a phase between the horizontal synchronization signal and the frequency-divided signal, a voltage-controlled oscillator whose oscillation frequency is controlled by an output of the phase-detection circuit, A frequency dividing circuit for dividing the output of the oscillator to output the frequency-divided signal, wherein the input signal detecting circuit determines the synchronization between the horizontal synchronizing signal and the frequency-divided signal and outputs the composite video signal. 2. The character signal synchronous reproduction circuit according to claim 1, wherein the presence / absence of an input is detected. 3. The input signal detection circuit counts the second clock generated during the horizontal synchronizing signal, and generates a determination result signal indicating whether or not the composite video signal has been input. 2. The character signal synchronous reproduction circuit according to claim 1, wherein the signal is output outside the period of the vertical synchronizing signal of the composite video signal.