KR930002088B1 - Apparatus for detecting non-standard image signal of tv - Google Patents

Abstract

The circuit detects non-standard video signal and prevents malfunction of detecting by stopping generating output of detection when noise exceeds a reference level. It includes a differential detector (10) for detecting the difference between current sync. and 1-field-previous sync., a signal level down section (32) for reducing the pedestal level detected by a pedestal level detector (31) to its signal level, an area integrating section (50) for integrating the output of the signal level down section (32), and a switching section (20) for switching normal video signal from the differential signal detector (10) and noise removed video signal.

Description

Non-standard video signal detection circuit

1 is a detailed circuit diagram showing an embodiment of a conventional non-standard video signal detection circuit.

2 is a timing diagram showing an operating state according to FIG.

3 is a block diagram showing an embodiment of a non-standard video signal detection circuit according to the present invention.

4 is an operating characteristic diagram showing the input / output states of the signal level down unit according to FIG.

5 is a detailed circuit diagram showing a pulse generator according to FIG.

6 is an operating characteristic diagram showing the output state of the pulse generator according to FIG.

FIG. 7 is a detailed circuit diagram illustrating a section integrator according to FIG. 3.

8 is a detailed circuit diagram of an output unit according to FIG. 3.

* Explanation of symbols for main parts of the drawings

10: difference signal detection unit 20: switching unit

30: signal detection circuit 31: pedestal level detector

32: signal level down part 40: pulse generating circuit

41: section detection section 42: clear pulse output section

43: clock pulse generator 50: interval integrator

60: comparator 70: output unit

100: switching control means D1 to D7, D71 to D7n: D type flip flop

COUNT: Counter ORl, OR71: Oagate

AND1: AND gate ADD: adder

CLR: Clear Pulse CLK: Clock Pulse

H: Horizontal synchronous signal V: Vertical synchronous signal

The present invention relates to a non-standard video signal detection circuit of a digital television, and more particularly, to clearly determine whether an input video signal is a standard signal or a non-standard signal, and to a non-standard signal of a video signal containing noise generated in a weak electric field region. The present invention relates to a non-standard video signal detection circuit capable of preventing a malfunction caused by an incorrect determination of.

In general, the most important thing in digital television is the clock system. That is, the clock system is most involved in displaying the processed image signal information in high quality. The clock system is locked according to a color subcarrier and is controlled by a burst locking clock generated by the PLL circuit and a line locking clock generated by the PLL circuit. The ratio of the color carrier fsc to the horizontal synchronization frequency f _H according to the video signal is 3.58. In the case of an NTSC standard signal, a burst locking clock having low jitter noise and easy demodulation of color signals can be used. .

However, when the ratio of the color subcarrier horizontal synchronization frequency of the video signal is not less than 3.58, the line locking clock for the best image processing should be used. That is, the color carrier of the video signal When the burst locking clock is used, the color carrier In this case, the line locking clocks must be used respectively for the best image processing.

In addition, the luminance luminance / color signal separation, which is a standard video signal, is processed by a motion adaptive processing method in order to improve image quality, and in the case of non-standard video signals, the degradation of the image quality can be prevented by separating luminance / color signals by a band pass filter. have.

Therefore, in order to process the input video signal without deterioration in image quality, it is first necessary to determine whether the input video signal is a standard signal or a non-standard signal.

The conventional solution for detecting the non-standard signal stores the presynchronization signal portion of one field in the memory unit 1 as shown in FIG. 1, and synchronizes the presynchronization signal with the one field presynchronization signal stored in this memory unit l. After comparing the signals, the difference components of the two signals are detected by the difference signal detection unit 2 as the difference signals as shown in FIG.

Here, FIG. 2 (a) shows the video input signal, and FIG. 2 (b) shows the field delay input signal.

The signal output from the difference signal detection unit 2 is waveform-shaped by the integrating unit 3, and is compared with a reference signal input by the comparing unit 3 and then output.

However, such a conventional solution is capable of detecting non-standard signals in a video signal in which the horizontal synchronization signal has a small jitter noise and a vertical synchronization signal has a large jitter noise. In this case, even if the synchronization signal between the fields is correctly synchronized, the standard video signal input by the input noise component is detected as a non-standard signal. Therefore, there was a problem that a malfunction occurs throughout the clock system.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to detect a noise higher than a reference value to a video signal input when a video signal input from a region of a weak electric field is a standard signal or a non-standard detection signal by a difference signal detector. The present invention aims to provide a non-standard video signal detection circuit capable of preventing a malfunction of the non-standard signal detection circuit due to a noise component generated in the weak electric field by blocking the output of the non-standard video signal.

A feature of the present invention for achieving the above object is to store the motor signal portion of a field in the memory unit according to the image signal applied from the outside, and compares the field synchronization signal and current synchronization signal stored in this memory unit A non-standard video signal including a difference signal detector comprising a difference component between the two signals, an integrator configured to waveform-shape the difference signal output from the difference signal detector, and a comparator for comparing and outputting the output signal of the integrator and a reference signal A detecting circuit comprising: a pedestal level detecting unit connected between an input terminal of the difference signal detecting unit and a switching unit input terminal of a rear stage, and detecting a pedestal level of the video signal when a noise component is mixed in the video signal; A signal level down part which lowers the detected pedestal level to bring down the overall signal level; A section integrator configured to receive an output signal of the bell-down section and accumulate waveforms during a pulse output section, and a plurality of inputs in one vertical synchronous pulse according to a vertical synchronous signal and a horizontal synchronous signal applied from the outside to the section integrator; The pulse generation circuit for applying the clear pulse output after being delayed by the set number of horizontal synchronization pulses and the clock pulse output after being delayed by 1H, and the accumulated video signal and the reference signal by receiving the output signal of the section integrator are compared. Switching control means having a comparator for outputting and accumulating and outputting the output signal of the comparator within a vertical synchronization pulse period; And a non-standard video signal detection circuit controlled by the switching control means to detect a non-standard video signal through a switching unit which switches and outputs the video signal from which the noise is removed and the normal video signal of the difference signal detection unit.

Hereinafter, with reference to the accompanying drawings an embodiment according to the present invention will be described in detail.

3 is a block diagram of an embodiment of a non-standard video signal detection circuit according to the present invention.

Here, a switching unit 20 for switching and outputting the difference signal is connected to an output side of the difference signal detection unit l0 that detects and outputs a difference between a field motor signal of the input image signal and a current synchronization. Switching control to detect the non-standard signal detection by the difference signal detection unit 10 by detecting that the video signal of the weak electric field area when the mixed noise of the input video signal between the input side and the switching unit 20 of the reference level or more Connect the means (l00).

Referring to the configuration of the switching unit control means 100 in more detail, the signal detection circuit 30 for detecting the DC component of the pedestal level of the input video signal is a reference set to the output side of the pedestal level detector 31. The signal level down part 32 is connected so that the level of the signal input by the signal is down.

On the other hand, the vertical synchronous pulse output from one vertical synchronous signal (V) by the output side of the signal level down unit 32, and the horizontal synchronous signal (H) and the vertical synchronous signal (V) to be input and horizontal Clear pulses are generated after a delay of any horizontal synchronizing pulse among the synchronization signals, and are output from the signal level down section 32 between the output side of the pulse generating circuit 40 where clock pulses are generated while one horizontal synchronizing pulse is generated. The signal accumulating is accumulated to the interval of the pulse signal output from the clock generation circuit 40 is connected to the interval integrating unit 50 for waveform shaping. A comparator 60 for comparing the noise level of the video signal accumulated and waveform-formed is connected to the output side of the interval integrating unit 50, and the output side of the comparator 60 is input than the reference noise level. When the noise level is high, the output unit 70 for outputting the input video signal to the weak electric field is connected.

5 and 6 show a detailed circuit of the pulse generating circuit 40 and the operation timing diagram of the non-standard signal detecting circuit according to FIG.

That is, as shown in FIG. 6 (a) from the input vertical synchronous signal V and the horizontal synchronous signal H, the input side of the section detection unit 41 in which one vertical synchronous pulse and a plurality of horizontal synchronous pulses are detected is provided. One vertical synchronization pulse is input by the section detection unit 41, and a clear pulse output unit 42 for generating a clear pulse CLR is connected after the input horizontal synchronization pulse is delayed by an arbitrary number. At the same time, the clock pulse output unit 43 for outputting the clock pulse CLK after the horizontal synchronous pulse according to the clear pulse CLR is output and delayed by 1H is connected.

In more detail, the configuration of the D-type flip-flop (D1) (D2) of the section detection unit 41 for detecting the vertical synchronization pulse from the input vertical synchronization signal (V) is connected in sequence, the D-type On the output side of the flip-flop D1, one vertical synchronous pulse is output by synchronizing the inverted output signal Q bar of the D-type flip-flop D1 and the output signal Q of the D-type flip-flop D2. The oragate OR1 of the section detection unit 41 is connected. A counter COUNTl of the section detection unit 41 that counts any number to delay any number of horizontal sync pulses input while one vertical sync pulse is input to the output side of the ORA gate ORl is connected. do.

The D-type flip-flop (D3) (D4) of the clear pulse output unit 42 is set to the output side of the counter (COUNT1) is set in the interval of the horizontal synchronous pulse is delayed by a set number, the D-type An output gate Q of the D-type flip-flop D3 and an inverted output signal Q-bar of the D-type flip-flop D4 are connected to an output side of the flip-flop D4. have.

On the other hand, the D-type flip flop (D5) of the clock pulse output unit 43 is latched to the other output side of the counter (COUNT) is latched horizontal synchronization pulse 1H more than the set value.

Here, the output signal of the AND gate AND of the clear pulse output unit 42 and the output signal of the D flip-flop D5 of the clock pulse output unit 43 are applied to the interval integrating unit 50 of FIG. do.

FIG. 7 is a detailed circuit diagram showing the section integrator 50 of FIG. 3, the configuration of which is shown.

An input signal whose signal level is down by the signal level down part 32 of FIG. 3 and an input signal delayed by the clear pulse CLR of the clear pulse output part 42 of the pulse generating circuit 40 are input. The D-type flip-flop D6 of the section integrating unit 50, to which the input signal is delayed by the clear pulse CLR input to the output side of the adder ADD to be added, is connected. Here, the output signal of the D flip-flop D6 of the interval integrating unit 50 is fed back to the adder ADD.

Also, on the output side of the adder ADD, the D-type flip-flop D7 whose output signal of the adder ADD is delayed by the clock pulse CLK of the clock pulse output unit 43 of the pulse generating circuit 40 is provided. Connected.

FIG. 8 is a detailed circuit diagram showing the output unit 70 of FIG. 3, and a plurality of D-type flip-flops D71 to D7n to which the signal output from the comparator 60 of FIG. 3 is sequentially delayed are connected. Each output side of the D71 to D7n is connected with an OR gate OR7 for outputting the low level only when the signals output from the D flip-flops D71 to D7n are simultaneously at the low level.

In the present invention configured as described above, when a video signal is input, a difference between one field pre-synchronization signal and a current sync signal is detected according to the video signal input by the difference signal detection unit 10 shown in FIG. The difference signal detected by the difference signal detection unit 10 is output through the switching unit 20 shown in FIG.

At this time, the input video signal is applied to the pedestal detector 3l of the signal detection circuit 30 of the switching control means 100 shown in FIG. 3 to detect the pedestal level from the input video signal. The pedestal level of the video signal output from the pedestal level detector 31 is applied to the signal level down unit 32 of the signal detection circuit 30 so that the input signal level is greater than or equal to the reference level. It goes down.

That is, when the signal level input to the noise component is high, the level of the signal input by the signal level down section 32 is lowered. The signal output from the signal level down unit 32 of the signal detection circuit 30 is applied to the interval integrating unit 50 shown in FIG. 3 to generate pulses from horizontal and vertical synchronization pulses. Signals input during the input period of the pulse output from the circuit 40 are accumulated and waveform shaped.

This process will be described in detail with reference to FIGS. 5 and 6, and the input vertical synchronization signal V is inputted by the D-type flip-flops D1 and D2 and the oragate OR1 of the section detector 41. One vertical synchronizing pulse (see FIG. 6 (a)) is detected, and the detected one vertical synchronizing pulse is input to the counter COUNT, and the counter COUNT counts the input horizontal synchronizing signal. At this time, if the set number of the horizontal synchronization signal is counted. According to the signal output from the counter COUNT, the clear pulse CLR as shown in FIG. 6 (b) by the D-type flip-flop D3 (D4) and the AND gate AND1 of the clear pulse output unit 42. Is output.

On the other hand, when the number of the horizontal synchronization pulses plus the number set in the counter (COUNT) is counted, the signal counted in the counter (COUNT) by the D-type flip-flop (D5) of the clock pulse generator 43 The clock pulse CLK as shown in FIG. 6C is output. In the section integrator 50, the video signals input during the section of the clear pulse CLR and the clock pulse CLK that are output from the pulse generating circuit 40 are accumulated and waveform-formed. That is, the signal leveled down in the signal level down section 32 of FIG. 3 is added to the adders ADD and D of the section integrating section 50 of FIG. 7 during the interval between the input of the clear pulse CLR and the clock pulse CLK. Accumulated by the flip-flop D6, the accumulated signal is output by the flip-flop D7.

The signal accumulated by the interval integrating unit 50 and waveform-formed and output is applied to the comparator 60 of FIG. 3, and the signal applied to the comparator 60 is output after being compared with a reference level signal. . 8, a signal output from the comparator 60 is applied to an output unit 70, and a plurality of D-type flip-flops D71 to D7n and an oragate OR2 of the output unit 70 are provided. The output signal of the output unit 70 is output to the low level only when the signals output from the comparator 60 are all low level during the vertical synchronization pulse.

In addition, the low level output from the output unit 70 is applied to the switching unit 20 to turn off the switching unit 20, so that the output of the signal output from the difference signal detection unit 10 is controlled.

That is, when the noise component is mixed into the entire video signal, the input video signal is detected by the pedestal level detector 31 of the signal detection circuit 30 of the switching control means 100 of FIG. The pedestal level detected by the signal level down unit 32 is down. And, the image signal input during the interval of the pulse output from the pulse generating circuit 40 is accumulated by the interval integrator 50, and compared with the signal accumulated by the comparator 60 and the reference level If the noise level of the input video signal is higher than the reference noise level, it is output at a low level. Therefore, the noise of the image input from the output signal of the comparator 60 is detected. At this time, the low level output by the comparator 60 is output to the low level through the output unit 70, the low level is output to the non-standard signal of the input image signal by controlling the switching unit 20 is turned off The output of the detected signal is controlled.

As described above, the present invention provides a switching control means for controlling the output of a signal in which a non-standard signal of a video signal is detected in order to prevent the video signal from being determined as a non-standard signal when a noise component is mixed in an input video signal. By connecting the unit to the difference signal detection unit for detecting the non-standard signal of the video signal, it is possible to prevent the video signal from being misjudged as a non-standard signal and to prevent the system from malfunctioning. It has an effect.

Claims (4)

The motor signal portion of the field is stored in the memory unit 1 according to the video signal applied from the outside, and the difference between the two signals is detected after comparing the current synchronization signal with the field pre-synchronization signal stored in the memory unit 1. A difference signal detector 2, an integrator 3 for waveform shaping the difference signal output from the difference signal detector 2, and an output signal of the integrator 3 and a reference signal In a non-standard video signal detection circuit composed of a comparator (4); A pedestal level detector 31 connected between the difference signal detector input stage and the switching stage input stage of the rear stage and detecting a pedestal level of the video signal when a noise component is mixed in the video signal; A signal level down part 32 which lowers the pedestal level to bring down the overall signal level, an interval integrator 50 which accumulates waveforms during the pulse output period by receiving the output signal of the signal level down part 32; After delaying the set number of horizontal synchronous pulses input in one vertical synchronous pulse according to the vertical synchronous signal and horizontal synchronous signal applied from the outside to the interval integrating unit 50 by a predetermined number and a delayed clear pulse 1H. A pulse generation circuit 40 for applying the output clock pulses and the output signal of the interval integrating unit 50 are accumulated and the accumulated image signal And a comparator comparing the signal (60), and switching control means (100) having an output section 70 that an output signal of the comparator 60 output is accumulated within a period vertical synchronizing pulses; The non-standard video signal is controlled by the switching control means 100 to detect the non-standard video signal through the switching unit 20 for switching and outputting the video signal from which the noise is removed and the normal video signal of the difference signal detection unit 10. Detection circuit. According to claim 1, wherein the pulse generating circuit 40 of the switching control means 100 is a section detection unit 41 for generating a vertical synchronous pulse and a horizontal synchronous pulse in accordance with a vertical synchronous signal and a horizontal synchronous signal applied from the outside, respectively. And a clear pulse output unit 42 connected to the output side of the section detection unit 41 and having a predetermined number of delayed horizontal synchronous pulses, and a clear pulse being generated, and connected to the output side of the section detection unit 41. Non-standard video signal detection circuit, characterized in that consisting of a clock pulse output unit 43, the clock pulse is generated after the horizontal synchronization pulse output from the clear pulse output unit 42 is delayed by 1H. The control unit 100 of claim 1, wherein the interval integrating unit 50 of the switching control unit 100 includes the image signal leveled down by the signal level down unit 32 and the clear pulse CLR output by the clock generation circuit 40. The clock generation circuit receives the adder ADD and the D-type flip-flop D6 and the video signal outputted through the adder ADD and the D-type flip-flop D6. And a D-type flip-flop (D7) for delaying again according to the clock pulse (CLK) output by the P-type and outputting the delayed video signal. The method of claim 1, wherein the output unit 70 of the switching control means 100 comprises a plurality of D-type flip-flops (D71 ~ D7n) for detecting the video signal output by the comparator 60 during the vertical synchronization pulse, And an oragate (OR2) output at a low level when the signals inputted to the plurality of gate input terminals are all low level by receiving the respective output signals of the plurality of D-type flip-flops (D71 to D7n). Non-standard video signal detection circuit.