JPS6272278A - Synchronizing signal separating device - Google Patents

Abstract

PURPOSE:To separate a synchronizing signal without always causing phase shift by transiting a slice voltage accordingly when a DC level of a composite video signal is fluctuated. CONSTITUTION:The DC level of a composite video signal is clamped to be constant in a clamp circuit 33. A clamp circuit 37 clamps the composite video signal only when a pulse signal being an output of a monostable multivibrator 36 exists. A comparator 38 outputs a high level signal only when an output voltage of a level shift circuit 42 is higher than the level of an output signal of the clamp circuit 37. Thus, a pulse signal is outputted during the synchroniz ing signal period and it is used as a synchronizing signal and led to an output terminal 43. Thus, since the synchronizing signal portion is sliced nearly at the same position, no phase shift is caused in the synchronizing signal being an output of the comparator circuit 38.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization signal separation device for separating a synchronization signal from a composite video signal.

[Technical background of the invention]

Generally, a synchronization signal separation device consists of a so-called clamp circuit that fixes the DC level of a video signal to a constant value, and a slice circuit that slices the clamped video signal at a DC level that is a predetermined level different from the clamp level. Specifically, for example, a circuit shown in FIG. 4 is known.

In FIG. 4I, a positive composite image signal 15 supplied from an input terminal 11 is supplied to the base of a transistor Q through an amplifier 12 and a capacitor 13. Transistor Q1 is configured as an emitter follower type, and an output signal is supplied from the emitter to the base of transistor Q2 via capacitor 14. A series circuit of a diode 15 and a capacitor 16 is connected to the base of the transistor Q2 and a reference potential point. Diode 15 and capacitor 1
The connection point 6 is connected to the connection point of voltage dividing resistors 17 and 18, and is set to a constant DC voltage. This resistance 1
A clamp voltage source is formed by 7.18, capacitor 16 and power supply Vcc, and capacitor 14 and diode 15
The clamp circuit includes: Therefore, the composite video signal supplied to the base of transistor Q2 is clamped at a voltage (Ec) that is the value of the clamp voltage source minus the forward voltage of diode 15. Transistor Q2 is differentially connected to transistor Q3, their mutual emitters are connected to a reference potential point via a resistor 19, and a load resistor 20 is connected to the collector of transistor Q3. Also, the base of transistor Q3 is connected to a voltage dividing resistor 21.2.
A constant voltage (Es) is supplied by the transistor Q2, and the transistors Q2 and Q3 are selectively conductive or nonconductive with respect to this voltage (Es) depending on the base voltage of the transistor Q2.

Therefore, this voltage (Es) is set to a level higher than the clamp voltage (Ec) by a predetermined level (thereby, the transistor Q3 becomes conductive only during the period biJ of the synchronization signal, and its collector voltage decreases. This causes the output The same signal is taken out from the terminal 23. In other words, this means that the synchronization signal of the composite video signal has been sliced, and a slice circuit is constituted by the transistor Qz and the Qa resistors 19 to 22, and the voltage ( Es) is the slice voltage.

[Problems with background technology]

FIG. 5 shows the operating waveforms in FIG. 4. Figure 5 (A)
indicates a composite video signal input to the base of the transistor Q2, and the leading end of the synchronizing signal sy is clamped with a voltage (Ec).

Further, the voltage (Es) is a slice voltage, that is, the base voltage of the transistor Q3, whereby the synchronizing signal shown in FIG. 2(B) is separated and guided to the output terminal 23.

Now, if the composite video signal is mostly occupied by black level signals as shown by the dotted line in FIG. 5(A), the clamp voltage (Ec) changes by only ΔE volts due to the impedance of the clamp circuit. At this time, as shown in the figure,
Since the video signal passes through amplifiers that limit various frequency bands before reaching the synchronization signal separation device, the video signal is transformed so that the rise and fall of the synchronization signal have a slope. Therefore, the result of slicing such a signal using the slicing voltage (Es) is as shown in Figure 5 (C). Compared to the normal Figure 5 (B), the out-of-phase synchronization signal is separated. That will happen. For this reason, when attempting to externally synchronize other signals using this synchronization signal, a problem has arisen in that the phase of the synchronization signal shifts.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a synchronization signal separation device that can separate synchronization signals without causing a phase shift.

[Summary of the invention]

The present invention achieves the above object by configuring the slice circuit so that when the clamp voltage of the clamp circuit that keeps the DC level of the composite video signal constant changes, the slice voltage of the slice circuit also changes according to the voltage fluctuation. It is.

[Detailed description of the invention]

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

The positive polarity composite video signal supplied to the input terminal 31 is amplified to a level sufficient for slicing in the subsequent slicing circuit, and is supplied to the first clamp circuit 33. This first clamp circuit 33 clamps the composite video signal so that the DC level is constant. In other words, the synchronization signal S
It is clamped so that the tip of y becomes the clamp voltage (Ec). The output of the first clamp circuit 33 is supplied to the slicing circuit 34, where it is sliced with a slicing voltage (Es) as shown in FIG. 2(A) and converted into the signal shown in FIG. 2(B). It is supplied to the first mono-multivibrator 35. The slice circuit of the first mono-multivibrator 35 is triaged at the rising edge of the output of 34, and is reset after a period of time slightly shorter than one horizontal scanning period, that is, at a timing that coincides with approximately the center of the next synchronization No. 15. Figure 2 (
Output the signal shown in C). The output of the first mono multivibrator 35 is supplied to the second mono multivibrator 36, and the second mono multivibrator 36 is tripped at the falling edge of the signal No. 13, and the corresponding synchronization signal period is It returns at the timing of termination f and outputs the signal shown in FIG. 2(D). This second mono-multivibrator 36
The output of is supplied to the second clamp circuit 37. The second clamp circuit 37 is connected to the second mono-multivibrator 36
Composite video No. 13 is clamped only during the period in which the output pulse signal exists. That is, the second clamp circuit 37 is a so-called sync-nap clamp circuit, and clamps the leading end of the synchronizing signal to a predetermined voltage. Second clamp circuit 37
The output of is supplied to the inverting input terminal of a comparator 38 constituted by an operational amplifier, and is also applied to a sample hold circuit 39. On the other hand, the output of the slice circuit 34 is also supplied to the third mono-multivibrator 40, and the mono-multivibrator 40 of the cabinet 3 is tri-inputted at the rising edge of the input signal shown in FIG. It returns to the position approximately at the front porch and outputs the signal shown in FIG. 4(E). The output of the third mono multivibrator 40 is further supplied to a fourth mono multivibrator 41,
The multi-vibrator 41 is tripped by the fall of the human input signal and returns in a short time, outputting the signal shown in FIG. 2(F).

This signal is supplied to the sample hold circuit 39 as a sampling pulse.

Since the output pulse signal of the fourth mono-multivibrator 41 is generated at the front porch position of the synchronizing signal, the sample and hold circuit 39 holds the voltage of the front porch. The output of this sample hold circuit 39 is lowered in level by a certain value by a level shift circuit 42 and is supplied to a non-inverting input terminal of a comparator 38. The comparator 38 outputs No. 16 at a high level only during a period when the output voltage of the level shift circuit 42 is higher than the level of the output signal of the second clamp circuit 37. Therefore, a pulse signal is output during the synchronization signal period, and the pulse signal is outputted to the output terminal 43 as a synchronization signal. That is, the comparator 38 functions as a slice circuit, and the output voltage of the level shift circuit 42 is used as a slice voltage.

In the device configured as described above, the contrast video signal is almost a black level signal of 1:! 1.
The DC level of the output of the clamp circuit 33 is as shown in Fig. 2 (
It fluctuates as shown by the dotted line in A). As a result, the output signal of each mono-multivibrator also fluctuates as shown by the dotted lines in FIGS. 752(B) to 2(F). However, even in this state, if the output pulse signal of the fourth mono multivibrator 41 is set to be located at the front porch of the synchronization signal, the output voltage of the sample and hold circuit 39 will be adjusted to the fluctuations in the DC level of the video signal. It changes accordingly. Therefore, the output voltage of the level shift circuit 42 similarly fluctuates, and as shown in FIG. 2(G), the slice voltage changes from the level (Es) shown by the solid line to a point! This results in a transition to the level (Es') shown in (Es').

This allows the synchronization signal period to be sliced by 1δ, which is approximately the same as when the DC level does not fluctuate.
There is no phase shift in the synchronized signals output from the comparator circuit 38.

In the embodiment shown in FIG. 1 described above, the g
Create a pulse for sync tip clamping and a sampling pulse for sampling the front porch from the synchronization signal obtained by M l, first perform sync tip clamping, then sample the front porch, and adjust the voltage and sync tip based on the level. By comparing the clamped belly-to-edge video signal, we are able to ensure that the slices are sliced at exactly the same part of the synchronization signal, but the point is that in relation to the level of the 70/top porch and the level of the tip of synchronization No. 11. It is only necessary to determine the slice level, and the sync tip clamp circuit can be omitted, for example, as shown in FIG. 3.

In the embodiment shown in FIG. 3, the output of the first clamp circuit 33 is sampled and held in a sample hold circuit 39 and is supplied to a comparator 38, and the first and second mono-multivibrators 35 generate clamp pulses. .36 and the second clamp circuit 37 are omitted.

Note that the front porch level is the same as the back porch level, and it is set as a so-called pedestal reference, so it doesn't matter which one you sample and hold, but in the case of a color video signal, the color burst signal is applied to the back porch. The front porch is preferable because of the overlap.

In addition, in order to operate the embodiment described above more reliably, an automatic gain control circuit that controls the level of the sync signal portion, that is, the amplitude from the pedestal portion to the sync tip, is constant, is installed in the front stage of the sync signal separation device. may be provided.

〔Effect of the invention〕

As described above, according to the present invention, when the DC level of the composite video signal fluctuates, the slice voltage is changed accordingly, so the synchronization signal can be separated without always causing a phase shift. A signal separation device can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, and FIG.
FIG. 4 is a circuit block diagram showing another embodiment of the present invention.
The figure is a circuit block diagram showing a conventional synchronizing signal separating device, and a signal waveform diagram for explaining the operation of the fifth nail. , 35.36.40.41... Mono multivibrator 38...
... Comparator agent Patent attorney Nori Chika Ken Yudo Uji Hiroshi J

Claims (1)

[Scope of Claims] A clamp circuit that fixes the DC level of a composite video signal, a sample hold circuit that samples and holds the pedestal level of the composite video signal output from the clamp circuit, and the level of the output signal of this sample hold circuit. and a comparison circuit that compares the voltage levels of the composite video signal output from the clamp circuit and the output signal of the level shift circuit, converts the comparison result into a binary signal, and outputs the result as a synchronization signal. A synchronous signal separation device characterized by having: