KR0160615B1 - Circuit for separating sync.-signals - Google Patents

Abstract

The synchronization signal separation circuit is intended to simplify and stabilize the circuit in an apparatus for processing a high quality video signal. A synchronization signal separation circuit for separating a synchronization signal of a composite video signal applied for this purpose; Negative pulse detection means for detecting a negative pulse of the synchronization signal of the composite video signal clamped to a predetermined reference level; Compound synchronous signal detecting means for detecting a compound synchronous signal by adjusting the width of the negative pulse detected by the negative pulse detecting means; Horizontal synchronous signal detection means for adjusting the pulse width of the output signal of the composite synchronous signal detection means and detecting the horizontal synchronous signal by a predetermined logical operation of the output signal of the composite synchronous signal detection means and the signal whose pulse width is adjusted; And a vertical synchronizing signal detecting means for adjusting the pulse width of the output signal of the horizontal synchronizing signal detecting means and detecting the vertical synchronizing signal by the predetermined logical operation with the output signal of the complex synchronizing signal detecting means.

Description

Synchronous Signal Separation Circuit

1 is a conventional composite synchronization signal separation circuit diagram.

2 is an output waveform diagram of FIG. 1 for a tri-level synchronous signal.

3 is a waveform diagram of a moving picture pulse within the vertical blanking period of the tri-level synchronous signal.

4 is a synchronization signal separation circuit diagram according to the present invention.

5 is an output waveform diagram of the circuit diagram shown in FIG.

* Explanation of symbols for main parts of the drawings

4: buffer 5: pedestal clamp circuit

6: negative polarity pulse detection means 7: complex synchronous signal detection means

8: horizontal synchronous signal detection means 9: vertical synchronous signal detection means

The present invention relates to a circuit for separating a synchronous signal of a video signal, and more particularly, to a synchronous signal separation circuit for separating a synchronous signal of a high-definition video signal using a tri-level synchronous signal.

A general video signal processing apparatus records and reproduces a synchronization signal of a video signal with a binary waveform, but processes a high quality video signal by a delay time in recording and reproducing a signal. For recording and reproducing signals, a three-dimensional waveform as shown in Fig. 2A is used. Accordingly, the circuit for separating the synchronization signal has been reconfigured to fit the three-value waveform.

FIG. 1 is a circuit diagram for separating the synchronous signal of a three-dimensional waveform which is mainly used. When a composite video signal having a three-dimensional waveform is applied, a pedestal clamp circuit 1 and a peak clamp circuit 2 are applied. Is applied. The pedestal clamp circuit 1 adjusts and outputs the potential of the pedestal level, which is a level between the video signal and the synchronization signal, so that the potential does not change, and the peak clamp circuit 2 outputs the negative peak level of the applied composite video signal. Adjust the output so that the potential does not change.

The signal output from the pedestal clamp circuit 1 is applied to the non-inverting input terminal (+) of the first comparator COM1 of the next stage. The first comparator COM1 outputs high only when the signal output from the pedestal clamp circuit 1 is greater than or equal to the pedestal level because the reference voltage is ② of FIG. 2A. Will output low. Ⓐ, which is a signal output from the first comparator COM1, is output as shown in FIG. However, there is a possibility that an error occurs in the phase detection of the positive pulse due to the hatched portion. Therefore, the peak clamp circuit 2, the second comparator COM2, the monostable multivibrator MM1, and the AND product AND1 perform accurate phase detection for the positive pulse. That is, the second comparator COM2, to which the signal output from the peak clamp circuit 2 is applied to the inverting input terminal (-), reaches a ① because the reference voltage is set to ①, the threshold level of the negative pulse. Until the low state is output, the negative pulse is detected by outputting high from point ① to point ① '. Therefore, ⓑ is a negative pulse. The monostable multivibrator MM1 adjusts the pulse width so that the output signal of the second comparator COM2 becomes high up to the threshold level of the positive pulse and starts the threshold level of the negative pulse as shown in FIG. A gate pulse having a period from the point to the point where the threshold level of the positive pulse ends is outputted. The first logical element AND1 performs a logical multiplication on the output signal of the first comparator COM1 and the monostable multivibrator MM1 and starts from the start of the pedestal level of the positive pulse as shown in FIG. The composite synchronization signals C and SYNC having a period up to this end point are output.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous signal separation circuit which further simplifies the conventional circuit made as described above and improves the circuit stability.

In order to achieve the above object, the present invention provides a synchronization signal separation circuit for separating a synchronization signal of a composite video signal to be applied; Compound synchronous signal detecting means for detecting a negative pulse of said synchronous signal of said composite video signal clamped to a predetermined reference level; Compound synchronous signal detecting means for detecting a compound synchronous signal by adjusting the width of the negative pulse detected by the negative pulse detecting means; The pulse width of the output signal of the composite synchronous signal detection means is adjusted, the output signal of the composite synchronous signal detection means and the pulse width, the output signal of the composite synchronous signal detection means and the predetermined signal of the pulse width is adjusted Horizontal synchronizing signal detecting means for detecting a horizontal synchronizing signal by a logical operation of? And a vertical synchronous signal detecting means for adjusting the pulse width of the output signal of the horizontal synchronous signal detecting means and detecting the vertical synchronous signal by a predetermined logic operation with the output signal of the complex synchronous signal detecting means. .

Next, the present invention will be described in detail with reference to the accompanying drawings.

3 is an enlargement of the moving picture pulse portion of the vertical retrace period for explaining the present invention.

4 is a circuit diagram of an image signal having a tri-synchronous signal as an embodiment of a synchronization signal separation circuit according to the present invention.

4 shows that when a composite video signal having a tri-level synchronization signal is applied, the pedestal level is set to a predetermined reference level by using the buffer 4 for removing the influence of other circuits and the output of the buffer 4 as an input signal. Detection means 6 for detecting the negative pulse of the synchronization signal using the pedestal clamp circuit 5 for clamping the signal, the signal output from the pedestal clamp circuit 5 as an input signal, and the detection means ( The composite synchronous signal detecting means 7 for detecting the composite synchronous signal using the negative polarity pulse detected in 6) as the input signal, and the composite synchronous signal using the signal output from the composite synchronous signal detecting means 7 as the input signal. The horizontal synchronous signal detecting means 8 for detecting the horizontal synchronous signal from which the moving picture pulse has been removed, and the vertical synchronous signal for detecting the vertical synchronous signal using the signal output from the horizontal synchronous signal detecting means 8 as an input signal. Detection means (9) It consists of.

In more detail, the negative pulse detecting means 6 connects the signal output from the pedestal clamp circuit 5 to the inverting input terminal (-) and the pedestal level (0 potential) to the non-inverting input terminal (+). When the threshold level V _thr is selectively applied, the third comparator COM3 for outputting the negative pulse and the output signal of the third comparator COM3 are applied so that the pulse width can be stabilized. The monostable multivibrator MM2 for controlling and outputting the control signal, and the signal output from the monostable multivibrator MM2 and the signal output from the third comparator COM3 to perform a logical multiplication. The logical multiplication device AND2 for controlling the potential and the low potential contact L are connected to the threshold level V _thr of the synchronization signal, and the high potential contact H is connected to the ground which is a pedestal level. Non-inverting input of the third comparator (COM3) It consists of a control switch (SW1) connected to the (+).

The combined synchronous signal detecting means 7 uses the output signal of the third comparator COM3 as one side input signal B and the other side input signal to the ground terminal to apply the pulse width of the negative pulse applied to the input terminal B. The non-inverted output signal of the monostable multivibrator MM3 and the monostable multivibrator MM3 is one input signal B, and the output signal of the negative polarity detecting means 6 is the other one input signal ( It consists of the monostable multivibrator MM4 for adjusting the pulse width of the output signal of the monostable multivibrator MM3 applied as A).

The horizontal synchronous signal detecting means 8 is a composite synchronous signal detected by the compound synchronous signal detecting means 7 connected to one input terminal B and a ground connected to the other input terminal A, and applied to the B input terminal. The monostable multivibrator MM5 for adjusting the pulse width of the output signal of the signal detecting means 7, the non-inverted output signal of the monostable multivibrator MM5 and the output signal of the combined synchronous signal detecting means 7 Logical AND operation, and logical AND element (AND3) for detecting the horizontal synchronization signal.

The vertical synchronizing signal detecting means 9 connects the horizontal synchronizing signal output from the horizontal synchronizing signal detecting means 8 to one input terminal A and the other input terminal B connects the supply power to the input terminal (A). A monostable multivibrator MM6 for adjusting the pulse width of the horizontal synchronous signal to be applied, and a logic sum element OR1 for logically logical operation of the inverted output signal of the monostable multivibrator MM6 and the output signal of the composite synchronous signal. ) And a supply power supply to one input terminal (B), and an output signal of the logic sum element (OR1) to the other input terminal (A) to adjust the pulse width of the output signal of the logic sum element (OR1) to adjust the inverted output stage. It consists of a monostable multivibrator (MM7) for outputting a vertical synchronization signal through.

FIG. 5 is an output waveform diagram of each part of the circuit diagram of FIG. 4, (A) is a composite video signal having a tri-level synchronizing signal, and (B) is a third comparator COM3 of the negative pulse detection means 6. As shown in FIG. (C) is an output signal of the non-inverted output end of the monostable multivibrator MM3 in the compound synchronous signal detecting means 7, and (D) is an output signal of the inverted output end of the monostable multivibrator MM3. (E) is an output signal of the non-inverting output stage of the monostable multivibrator (MM4), (F) is an output signal of the inverting output stage of the monostable multivibrator (MM4), and (G) is a horizontal synchronous signal detecting means. (8) is an output signal of the non-inverting terminal of the monostable multivibrator MM5, (H) is a horizontal synchronous signal detected by the horizontal synchronous signal detecting means 8, and (I) is a vertical synchronous signal detecting means ( 9) is the signal output from the non-inverting output terminal of the monostable multivibrator MM6, and (J) is vertical And the output signal of the logical product element (OR1) in the signal detecting means (9), (K) is a vertical synchronization signal detected by the vertical synchronizing signal detecting means (9).

Next, the operation of FIG. 4 will be described with reference to FIGS. 3 and 5.

When the composite video signal including the tri-synchronous signal is applied as shown in FIG. Through a constant output so that the DC value of the pedestal level of ② in Figure 2 does not change. Here, the internal configuration of the pedestal clamp circuit 6 is as known. And f _H in Fig. 5A is one horizontal scanning period.

When the signal output from the pedestal clamp circuit 5 is applied, the negative pulse detecting means 6 detects only the negative pulse through the third comparator COM3. That is, the output signal of the pedestal clamp circuit 5 applied to the inverting terminal (-) is compared with the level of the reference potential applied to the non-inverting terminal (+). At this time, the level of the reference potential is selectively applied through the control switch SW1. The control switch SW1 connects the threshold level (point 1 in FIG. 2) of the synchronization signal to the low contact point L, and grounds the pedestal level ground to the high contact point H. The level of the reference potential is controlled to be a threshold level. Accordingly, the third comparator COM3 outputs a low signal in a signal section above a threshold level as shown in FIG. 5B for a waveform applied as shown in FIG. 5A and a high signal in a signal section below a threshold level. Output

That is, when the signal applied to the inverting terminal (-) becomes the point (①) of FIG. 2, the third comparator COM3 switches the output signal from low to high. The output of the third comparator COM3 is applied to the composite synchronous signal detecting means 7 of the next stage and to the one input terminal of the monostable multivibrator MM2 and the AND product AND2. Since the signal output from the monostable multivibrator MM2 is also high when the signal output from the third comparator COM3 becomes high, the logical AND device AND2 outputs high, and the control switch SW1 is high. After switching to the contact point L, the reference level of the third comparator COM3 is changed from the threshold level to the pedestal level after detecting the threshold level to detect the negative pulse. Here, the monostable multivibrator MM2 is configured to change the reference level of the third comparator COM3 back to the threshold level after the reference level of the third comparator COM3 is changed to the pedestal level and before the next threshold level is detected. The width of the pulse applied from the third comparator COM3 is adjusted and output to the logical AND device AND2. When the output signal of the monostable multivibrator MM2 becomes high, the logical AND device AND2 outputs a low logic L to the control switch SW1 to control the low contact L to be switched.

When the negative pulse detected by the negative pulse detection means 6 is applied as shown in FIG. 5B, the monostable multivibrator MM3 outputs the third comparator COM3 as shown in FIG. 5C. Operate at the rising edge of the waveform (e.g., rising edge of the pulse by the ④ pulse of the moving picture pulse in the vertical retrace period of FIG. 3) to have a constant pulse width of T1 so as to go low in the ⑧ section of the shown moving picture pulse. Adjust the output. At this time, the output is made through the non-inverting output stage. The monostable multivibrator MM4 becomes active during the period when the output signal of the monostable multivibrator MM3 applied to the (B) input terminal is high, and is output from the third comparator COM3 applied to the (A) input terminal. The high logic signal is output at the falling edge of the signal, and the high state is maintained so as to have a pulse width of T2 as shown in the figure. Therefore, the composite synchronization signal as shown in Fig. 5E is detected. This is a positive composite synchronous signal, and the signal output from the inverting output terminal of the monostable multivibrator MM4 as shown in FIG. 5F is a negative composite synchronous signal.

The horizontal synchronous signal detecting means 8 applies the pulse width T3 to the monostable multivibrator MM5 as shown in FIG. 5 (G) when the positive mixed synchronous signal detected by the composite synchronous signal detecting means 7 is applied. Adjust and output through the non-inverting output terminal. That is, the monostable multivibrator MM5 outputs high logic at the rising edge of the pulse applied to the input terminal (B). This high logic period is used to remove one moving picture pulse in the vertical retrace period per horizontal scanning period. Is set.

The AND product AND3 is a positive-polar compound synchronous signal output from the monostable multivibrator MM4 as shown in FIG. 5E and a ratio output from the monostable multivibrator MM5 as shown in FIG. 5G. The inverse output signal is logically multiplied to output a horizontal synchronous signal from which a moving picture pulse is removed from the composite synchronous signal as shown in FIG.

The vertical synchronous signal detecting means 9 converts the high level signal from the falling edge when the horizontal synchronous signal detected by the horizontal synchronous signal detecting means 8 is applied to one input terminal A of the monostable multivibrator MM6. As shown in (I) of FIG. 1, the pulse width is adjusted by T4 to be output to the logical sum element OR1. Here, (I) of FIG. 5 is an output signal of the non-inverting terminal of the monostable multivibrator MM6, and the logic state is different from that described above. The logical sum element OR1 performs a logical sum of the inverted output signal of the monostable multivibrator MM6 and the inverted output signal of FIG. 5 (F), which is an inverted signal output from the composite synchronous signal detecting means 7, to be vertical as shown in FIG. Outputs from the second moving picture pulse among the moving picture pulses during the retrace period. The monostable multivibrator MM7 converts the falling edge of the output signal of the logic sum element OR1 to low logic when the output signal of the logic sum element OR1 is applied through one input terminal A to convert the moving pulse section into one. In order to make it, the pulse width is adjusted like the T5 of (K) of FIG. In this case, since the vertical synchronization signal is generated based on the second moving picture pulse, it is always stably detected regardless of the difference in the 0.5H period due to the odd and even fields.

As described above, the present invention has the advantage of simplifying and stabilizing the circuit by detecting the synchronization signal by adjusting the pulse width in the detection of the tri-level synchronization signal used in the high quality video signal processing apparatus, and the time delay generated during the synchronization separation. There is an advantage that can be reduced.

Claims (4)

A synchronization signal separation circuit for separating synchronization signals of a composite video signal; Negative pulse detection means (6) for detecting a negative pulse of said synchronization signal of said composite video signal clamped to a predetermined reference level; Compound synchronous signal detecting means (7) for detecting a compound synchronous signal by adjusting the width of the negative pulse detected by the negative pulse detecting means (6); The pulse width of the output signal of the compound synchronous signal detecting means 7 is adjusted, and the horizontal synchronous signal is detected by a predetermined logical operation of the output signal of the compound synchronous signal detecting means 7 and the signal whose pulse width is adjusted. Horizontal synchronous signal detecting means (8) for carrying out; Vertical synchronous signal detecting means for detecting the vertical synchronous signal by a predetermined logic operation with the output signal of the composite synchronous signal detecting means 7 by adjusting the pulse width of the output signal of the horizontal synchronous signal detecting means 8 ( 9) including 2. The comparator according to claim 1, wherein the negative pulse detecting means (6) is configured to detect the negative pulse by comparing any one of the pedestal level and the threshold level of the synchronization signal with the reference signal. ), A control switch SW1 for selectively switching any one of the pedestal level and the threshold level, and for controlling the switching of the control switch SW1 by an output signal of the comparator COM3. After the reference level of the logic device AND2 and the comparator COM3 are set to the pedestal level, the pulse width of the input level of the logic device AND2 is changed so that the reference level is changed before the next threshold level is detected. A synchronization signal separation circuit, characterized in that consisting of a pulse width adjusting means for adjusting (MM2). 2. The negative polarity pulse detection according to claim 1, wherein the complex synchronous signal detecting means (7) detects only the negative pulse section corresponding to the horizontal synchronizing pulse from the signal output from the negative polarity pulse detecting means (6). A first pulse width regulator (MM3) for adjusting the pulse width output from the means (6) and the first pulse width for outputting the composite synchronous signal according to a signal output from the negative pulse detection means (6). And a second pulse width controller (MM4) for adjusting the pulse width of the signal output from the controller (MM3). 2. The third pulse width adjusting means (MM6) according to claim 1, wherein said vertical synchronizing signal detecting means (9) adjusts a signal output from said horizontal synchronizing signal detecting means to a predetermined pulse width within one horizontal synchronizing pulse period (MM6). ), A logic element OR1 for logically processing the inverted output signal of the third pulse width adjusting means MM6 and the negative composite synchronous signal output from the composite synchronous signal detecting means 7, and the logic A fourth pulse width adjusting means (MM7) for adjusting the pulse width such that a vertical synchronization signal is generated based on a second moving pulse among the moving pulses in the vertical retrace period of the composite video signal by the output signal of the element OR1; Sync signal separation circuit, characterized in that made.