JPH037188B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a framing code detection circuit that is effective for use in systems that receive and reproduce television signals containing character information.

2. Description of the Related Art Among communication systems, there is a system in which, for example, character information is transmitted as digital information, and this is sampled using sampling pulses on the receiving side. In this case, the sampling data is processed according to the type of data. For example, a teletext packet sent by teletext broadcasting consists of a 16-bit "10101010101010" clock line-in signal, an 8-bit "11100101" framing code, followed by a 272-bit data section, etc. As will be described later, the framing code indicates the starting position of the data, and by detecting the framing code with the detection circuit, the reference position in the data string can be determined.

When performing data processing, it is important to accurately detect the above-mentioned framing code in order to perform data processing without error. A framing code detection circuit used in a conventional teletext signal processing apparatus is configured as shown in FIG. Reference numeral 11 denotes an input terminal, into which a waveform-shaped character multiplex signal is input. This character multiplex signal is
The data is processed using sampling pulses in order to be converted from serial to parallel in the shift register 12. A sampling pulse is applied from input terminal 13. Of the data stored in the buffer register 12, the framing code is detected by the detection unit 14. The detection signal obtained from the detection section 14 is input to the gate circuit 15. A framing signal gate pulse and a teletext packet extraction gate pulse are input to this gate circuit 15 through input terminals 16 and 17. The framing signal gate pulse usually has a period of about 10 bits that masks the framing code, and the teletext packet extraction gate pulse is a pulse that masks the horizontal scanning period on which the teletext multiplex signal is superimposed. The framing detection signal is led out to the output terminal 18 through the gate circuit 15 only when the above-mentioned framing signal gate pulse and teletext packet extraction gate pulse are input.

FIGS. 2a to 2e are operation signal waveform diagrams of the above circuit. In Figure 2a, H is a horizontal periodic signal;
19 is a burst signal, CRI is a clock run-in signal, FC is a framing code, and 20 is a data section. Further, FIG. 2b shows the output pulse of the detection section 14, and FIG. 2c and d show the framing signal gate pulse and the teletext packet extraction gate pulse. Further, e in the same figure shows the final detection signal appearing at the output terminal 18.

According to the above-mentioned conventional framing detection means, if the detection unit 14 cannot detect the framing code due to disturbance such as impulse noise, the reference for the data reading start timing becomes unclear, and data is not captured. As a result, missing lines on the display screen occur in teletext broadcasting using the pattern transmission method, and missing lines on the display screen occur in the code transmission method. Furthermore, if a wrong location is assumed to be a framing code due to disturbance, a location shifted by N bits (N is a positive integer) is read as data, resulting in character shifts and a large amount of unknown data.

This invention was made to deal with the above-mentioned situation, and even if the framing code cannot be detected due to disturbances such as impulse noise, or if the wrong location is considered to be the framing code, data reading will start. It is an object of the present invention to provide a framing code detection circuit that can output a reference pulse at regular timing and ensures perfect data processing.

Embodiments of the present invention will be described below with reference to the drawings. First, although the present invention was used as an example of its application in a teletext signal processing device, it is of course applicable to all communication systems.

To further explain the format of the television signal used in teletext broadcasting, this format is set as shown in FIG. 3a and 3b show the vertical blanking period portions of the first field and the next field of the composite video signal, where V is a vertical synchronizing signal.

Teletext packets 21 and 22 are set at the rear of this vertical retrace period, for example, at the 20th H (H: one horizontal period) after the previous field ends. The format of this teletext packet is set as shown in FIG. 3c. H is a horizontal synchronization signal, and 25 is a color burst. The teletext packet 22 includes a header section 26,
It is formed by the information section 27. This teletext packet 22 is shown in more detail in FIG. 3d.

That is, the header section 26 receives the clock run-in signal CRI and the framing code.
It consists of FC, Identification Eye Code IDC, etc.

The types of teletext packets 22 include control packets, color code packets, and pattern data packets. The information part of the control packet contains data indicating the content that will be sent from now on. For example, as shown in Figure 3d, program codes (program numbers) PC1, DC2, Contains page numbers PA1, PA2, etc. In addition, the information section of the color code packet and pattern data packet includes a third
As shown in Figure e, color data, pattern data, etc. are included.

In the header section 26, the clock run-in signal CRI is a signal for adjusting the phase of the clock pulses necessary for sampling the data in the teletext packet. The framing code FC is a code that indicates the beginning of data. The identification eye code IDC indicates the display format or transmission signal format, and is a code for identifying when a mixture of programs in various display modes is being transmitted.

The teletext packets described above are processed, for example, by a system as shown in FIG. 3
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 32. The video-detected composite video signal is input to a waveform shaping circuit 33 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 41 that separates a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 41 are sent to the vertical position counter 4.
2 is input. This vertical position counter 42 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
By counting the numbers, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is superimposed.

The sampling pulse obtained by the vertical counter 42 is input to the waveform shaping circuit 33. As a result, the waveform shaping circuit 33 extracts the teletext packet described in FIG. 1 and shapes its waveform. The output obtained from this waveform shaping circuit 33 is input to a sampling circuit 34 and also to a clock run-in signal detection circuit 36.

The clock run-in signal detection circuit 36 extracts the clock run-in signal CRI shown in FIG.
This clock pulse generating circuit 37 has the function of generating continuous clock pulses in synchronization with the clock run-in signal. Continuous clock pulses output from the clock pulse generation circuit 37 are input to the sampling circuit 34 and used as data sampling pulses.

In the sampling circuit 34, various types of data as shown in FIG. The output of the sampling circuit 34 is also input to a framing code detection circuit 38.
The framing code detection circuit 38 performs detection by comparing a predetermined framing code with the input code, detects a point where the codes completely match, and detects the beginning of data in the buffer memory. This is what you set. Framing code detection circuit 38 is driven by clock pulses from horizontal position counter 43, for example.

The horizontal position counter 43 is reset by the horizontal synchronization signal H from the synchronization separation circuit 41, and counts the clock pulses from the clock pulse generation circuit 37. This horizontal position counter 4
The count information of 3 is also added to the address circuit 44. Further, this address circuit 44 includes:
The previous vertical synchronization signal is also input. This address circuit 44 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal.

As described above, the contents of the teletext packet are stored in the buffer memory 35 when the teletext packet arrives. The data stored in this buffer memory 35 is processed by a microcomputer.

Central processing unit (hereinafter referred to as CPU) 50
decodes the data contents of the buffer memory 35. For example, what is the data format?
What the program is like.

For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 60. The weather forecast program is specified by the program code shown in FIG. For example, the program code
Assuming that the data of PC1 is sending the weather forecast, this program code PC1 is
The calculation is processed in . As a result, if the data in the program code PC1 matches the data specified from the keyboard 60, it is determined that the data in the buffer memory 35 is data for a weather forecast. A command signal for reproducing the weather forecast specified from the keyboard 60 is stored in a random access memory (hereinafter referred to as RAM).

The weather forecast pattern data read from the buffer memory 35 is finally stored in the pattern memory 53 as character data and symbol data.
The color data is stored in color memory 54.

The data read from the buffer memory 35 is itself stored in the pattern memory 53 as character data or symbol data, but if the transmission method is a code transmission method, the data read from the buffer memory 35 is decoded and read. Predetermined character data, that is, characters, symbols, and graphic data may be read out from an only memory (hereinafter referred to as ROM) and stored in the pattern memory 53 or the like. Therefore, a character ROM 59 is further provided.

As mentioned above, character, symbol, and graphic data are stored in the pattern memory 53 based on the data derived from the buffer memory 35.
If a teletext packet in a vertical period is extracted only once, sufficient data for character display cannot be obtained. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 53.

When data is stored in the pattern memory 53 and color memory 54, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored.

When the data stored in the pattern memory 53 and color memory 54 are read out and displayed, the data in the pattern memory 53 is sent to the pattern decoder 55, and the data in the color memory 54 is sent to the color decoder 56 by direct current. is converted to
The output interface 57 synthesizes the signals.

Then, it is combined with the composite video signal in a combining circuit 58. Pattern memory 53, color memory 54
The data read timing is based on a command signal from the CPU 50. The CPU 50 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 44. If this address data matches the desired display specification data set in RAM52,
Read signals corresponding to these address data are applied to pattern memory 53 and color memory 54.

The display instruction data is included in a program stored in the RAM 52, and various display formats can be set according to changes in the display instruction data and program switching.

The teletext signal is processed as described above, and the framing code detection circuit 38 of the present invention is constructed as shown in FIG. Parts corresponding to those in FIG. 4 are given the same reference numerals and will be explained.
1 is input.

Furthermore, the data is also input to the specific code detection section 67. The framing code detection section 61 performs a comparison operation between preset data and input data, and when both data match, a match pulse is obtained, which is sent to the gate via an OR circuit 62. It is input to the circuit 63. The sampling circuit 34 has an input terminal 3.
A sampling pulse from a clock pulse generation circuit 37 is inputted via ₄₁ . The gate circuit 63 receives a framing signal gate pulse through an input terminal 64 and a teletext packet extraction gate pulse through an input terminal 65.
The gate circuit 63 can derive the detection pulse on the input side to the output terminal 66 only when the framing signal gate pulse and the teletext packet extraction gate pulse are input to the input terminals 64 and 65. The framing signal gate pulse has a pulse width of about 10 bits to mask the framing code, and the teletext packet extraction gate pulse has a pulse width of enough to mask the horizontal scanning period on which the teletext multiplex signal is superimposed. have These gate pulses are created using the outputs of the horizontal position counter and vertical position counter.

Next, the specific code detection unit 67 detects a specific code that all teletext packets have in common, such as a clock line-in signal "1010101010101010" or the last four bits of the clock line-in signal and the first four bits of the framing code.
It is set to output a pulse when bit "10101110" is detected.

Therefore, the framing code detection section 6
The pulse timing obtained from 1 and the pulse timing obtained from the specific code detection section 67 are naturally different.

The output of the specific code detection section 67 is sent to the AND circuit 6
8 is applied to one input terminal of the 8. Further, the other input terminal of this AND circuit 68 is connected to the input terminal 6
A specific code gate pulse is input via 9. This specific code gate pulse is also generated using the output of the horizontal position counter or vertical position counter, and is set in the specific code detection section 67 to the extent of masking the specific code to be detected. It's a pulse.

The output of the AND circuit 68 is then applied to the set terminal of the flip-flop circuit 70 and to the reset terminal of the counter 72.
The reset terminal of the flip-flop circuit 70 is
A reset pulse is applied via input terminal 71. This reset pulse is also generated using the outputs of the horizontal position counter and vertical position counter, for example, and is generated before the specific code arrives. That is, the reset pulse is generated at the end of the horizontal scan period. The counter 72 is reset by a specific code detection pulse output from the AND circuit 68, and counts data sampling pulses from the input terminal ₃₄₁ . This counter 72 is used to adjust the temporal position of a specific code. When the count value of this counter increases and the timing for detecting a framing code is reached, the count value at that time is detected by a decoder 73, and the count value at that time is detected by a decoder 73. A pseudo framing code detection pulse is generated, and this pseudo framing code detection pulse is applied to the second input terminal of the AND circuit 74. The flip-flop circuit 7 has a first input terminal of the AND circuit 74.
An output of 0, that is, a set output Q is added. As a result, if a specific code is detected,
A pseudo framing code detection pulse is output from the AND circuit 74 at the timing when the framing code detection pulse is obtained after a certain period of time from the detection point, and this is outputted via the OR circuit 62 and the gate circuit 63. and is led out to the output terminal 66.

6A to 6H are signal waveform diagrams of various parts in the above circuit when the framing code and the specific code are normally detected. Figure a shows the clock run-in signal CRI and the framing code FC. 4B shows the output obtained from the detection section 61, and FIG. 1C shows the output obtained from the detection section 67. Also, d in the same figure shows the flip-flop circuit 70.
The state of the set output Q is shown in FIG. Further, g in the same figure is a framing signal gate pulse applied to the input terminal 64, and h in the same figure is a framing signal gate pulse applied to the input terminal 64.
is the framing code detection pulse to be used available at output terminal 66.

Next, in FIGS. 7a to 7h, the framing code FC is disturbed due to disturbances such as impulse noise, and the framing code detection section 61 detects
The signal waveforms of each part are shown when the framing code cannot be detected. Figure a shows a state in which noise 75 is mixed in the framing code FC part. In such a case, no detection pulse is obtained from the framing code detection section 61, as shown in FIG. However, if the specific code detection pulse is obtained as shown in c of the figure, the set output Q of the flip-flop circuit 70 is obtained as shown in d of the figure, and the counter 72 is reset and receives the data sampling pulse. Because it counts,
As shown in figure e, a pseudo-framing code detection pulse is obtained. And OR circuit 62
The output shown in figure f is obtained from output terminal 6.
6, the framing code detection pulse shown in h of the figure is obtained. In the figure, g is a framing code gate pulse applied to the input terminal 64.

According to the above-described framing code detection circuit of the present invention, instead of using the detection pulse obtained from the detection unit 61 as it is as a time reference for starting data reading as in the conventional case, a specific code shared by all packets is detected, This is time-adjusted to the generation timing of the framing code detection pulse, and the regular framing code detection pulse and the time-adjusted pseudo-framing code detection pulse are extracted through an OR circuit. Even if the code cannot be detected due to disturbance, as long as the specific code is detected, the accurate data reading reference time can be determined. With this, it is possible to significantly improve problems such as missing lines on the display screen.

As described above, the present invention provides a framing code detection circuit that obtains a pseudo framing code detection pulse at a regular time position and ensures perfect data processing even when the framing code cannot be detected due to disturbance. can.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional framing code detection circuit, Fig. 2 a to e are operating signal waveform diagrams of the circuit in Fig. 1, and Fig. 3 a to e are diagrams of television signals handled in teletext broadcasting. FIG. 4 is a configuration explanatory diagram showing a teletext signal processing device; FIG. 5 is a configuration explanatory diagram showing an embodiment of the present invention; FIGS. 6 a to h, and FIGS. 7 a to h. are operation signal waveform diagrams shown to explain the operation of the circuit of the present invention. 61...Framing code detection unit, 62...
OR circuit, 63... Gate circuit, 67... Specific code detection section, 68, 74... AND circuit, 72...
...Counter, 73...Decoder.

Claims (1)

[Claims] A framing code indicating a reference position for sampling data transmitted for each packet is converted into parallel data using a sampling pulse, and this is compared with a predetermined code to determine the first framing. a framing code detection means for obtaining a code detection pulse; and a specific code commonly included in all packets of the transmitted data;
A specific code that is earlier in time than the framing code and excludes this framing code or includes a part of the beginning of the framing code is converted in parallel, and is compared with a predetermined code to determine the specific code. a specific code detection means for detecting a specific code detection pulse and obtaining a specific code detection pulse; means for outputting as a second framing code detection pulse; and setting a logical sum output of the pseudo second framing code detection pulse and the first framing code detection pulse to start reading data in a data reading unit. 1. A framing code detection circuit comprising: means for outputting a reference pulse as a reference pulse.