JP2540325Y2 - Closed caption broadcast receiver - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the improvement of a closed caption broadcast receiving apparatus for the deaf in the United States, and more particularly to a closed caption in which a shift register temporarily holding extracted caption data is improved. The present invention relates to a broadcast receiving device.

[0002]

2. Description of the Related Art Closed caption broadcasting (CLOSED CAP) for displaying conversations, announcements, and the like in a television broadcast program as captions for a deaf person on a television screen.
TION) is taking place in the United States. This is similar to teletext broadcasting in Japan, in which data is transmitted by being superimposed on a vertical retrace period of a video signal. The transmission of the data is a code system, and when displaying characters, a character generator (character generator) is prepared inside the receiver to prepare characters. As a result, it is possible to instantaneously display the code only by sending a code (code) from the broadcast station. The display mode is roughly classified into two types, a text mode (TEXT MODE) and a caption mode (CAPTION MODE). In the text mode, a maximum of 15 lines × 32 characters can be displayed at the center of the television screen, and in the caption mode, the upper and lower sides of the display range, that is, between 1 to 4 columns and 12 to 1 column.
Display is possible only for five columns. The data of the closed caption broadcast is superimposed in the vertical blanking period 21H (H is a horizontal scanning period), and the enlarged portion is as shown in FIG. Composite signal of 21H eyes shown in FIG. 2 (b) includes a color burst signal of 3.58MH _Z, 5
03KHz _Z run-in clock and caption data.
As shown in (b), a 3-bit start bit, 7-bit data, a parity bit of the data, a 7-bit data,
And a parity bit of the data. Fig. 2 (b)
8-bit data including 1 parity bit (1 byte)
Is transmitted as a unit, and in addition to the above-described character code, a command (command) for determining the position (row and column) and color of the character is transmitted.

[0003] As a receiver of this closed caption broadcast, one as shown in FIG. 3 is conceivable. The television broadcast signal on which the data of the closed caption broadcast is superimposed is received by the antenna (101) of FIG. 3, is tuned by the tuner (102), and is then amplified by the IF (intermediate frequency) amplifier circuit (103). It is detected. The detected video signal is processed by a Y / C (luminance / chroma) processing circuit (104), and an RGB primary color signal is applied to an RGB switching circuit (105).

[0004] Further, from the video signal from the IF amplifier circuit (103), only the caption data is extracted by the extraction circuit (106) and applied to the decoder (107). The decoder (107) performs parity check, display determination, decoding, and the like of caption data. The decoded caption data is applied to a character generator (108) and processed so that a desired character can be displayed at a desired position. Then, according to the processing, R, G, and B primary color signals are generated from the character generator (108), and the output control circuit (10
9) is applied to the RGB switching circuit (105), and the caption characters are displayed on the original television screen.

[0005]

The relationship between the sampling circuit (106) and the decoder (107) in FIG. 3 is shown in detail in FIG. From the extraction circuit (106) in FIG. 4, the caption data shown in (b) and (c) in FIG. 5 and a clock signal for detecting the caption data are applied to the decoder (107). FIG. 5A shows the timing of the horizontal synchronization signal. The caption data of FIG. 5B must be written to the 16-bit shift register 110 by the clock signal of FIG. 5C, but the clock signal is transferred to the 16-bit shift register 110 only during the period in which the caption data exists. ). For this purpose, the vertical synchronizing signal and the horizontal synchronizing signal are taken in from the terminals (111) and (112), and the shift prohibiting circuit (113) creates the shift prohibiting signal shown in FIG. The 16-bit shift register (110) is operated. By doing so, the caption data of FIG. 5B can be taken into the 16-bit shift register (110). However, a vertical deflection output signal and a horizontal flyback pulse are applied to the terminals (111) and (112).
Since these signals have a delay time, there is a problem that the signal of FIG.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal in a television signal, and a synchronization separation circuit for separating the synchronization signal from the synchronization separation circuit. A PLL circuit for locking to a horizontal synchronization signal,
A counter which is reset in response to a vertical synchronization signal from the synchronization separation circuit and counts an output signal of the PLL circuit; and a gate corresponding to a caption data period in accordance with the output signal of the counter and the output signal of the PLL circuit. Gate pulse generating means for generating a pulse, a comparator for extracting caption data in a television signal, a shift register for capturing caption data from the comparator according to a clock signal from the PLL circuit, and a shift register And output control means for outputting the clock signal applied to the gate pulse generation means only during the period of generation of the output gate pulse of the gate pulse generation means.

[0007]

According to the present invention, a gate pulse is generated according to an output signal of a PLL circuit locked to a horizontal synchronization signal from a synchronization separation circuit. The gate pulse is generated corresponding to a period during which the caption data exists, and transfers the clock signal and the data to the shift register only during the period.

[0008]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.
(114) is a synchronization separation circuit for separating the horizontal synchronization signal (H) and the vertical synchronization signal (V) from the video signal of the IF amplification circuit (103), and (115) is caption data from the video signal of the IF amplification circuit (103). , A comparator ( 116 ) is a phase comparator (117), a low-pass filter (118), a VCO (119), and a frequency divider (1).
A PLL circuit (20) counts a signal of 2f _H (f _H is a horizontal synchronizing signal frequency) from the frequency divider (120) as a clock signal, and outputs a vertical signal from the synchronizing separation circuit (114). A counter reset in response to a synchronization signal; and (122) an AND gate for generating a gate pulse corresponding to a caption data period in accordance with a divided output of the frequency divider (120) and an output signal of the counter (121). , (123) are 32 from the VCO (119)
first switch for applying a clock signal f _H to the decoder (107), (124) is a second switch for applying the output signal of the comparator (115) to the decoder (107).

In FIG. 1, the same circuit elements as those in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof will be omitted.
VCO of the PLL circuit (116) (119), the center frequency is set to 32f _H. 32f _H is a value for reading out the caption data, and the frequency divider (120)
Finally, the frequency is divided to the frequency f _H and the phase comparator (11
7) is applied. On the other hand, the phase comparator (117) includes:
Since the horizontal synchronization signal is applied from the synchronization separation circuit (114), the PLL circuit ( 116 ) locks to the horizontal synchronization signal. Therefore, the oscillation output signal of the VCO (119) is
This is locked to the phase of the horizontal synchronization signal shown in FIG. From the frequency divider (120), the first frequency-divided output signal φ ₁
Signal 2f _H is applied to the counter (121) as,
Also, as the second frequency-divided output signal φ ₂ , a pulse at the timing of extracting caption data as shown in FIG. 6B is applied to the AND gate (122). The counter (121) is reset according to the vertical synchronization signal from the synchronization separation circuit (114) and starts counting. Then, “H” is set during the 21H horizontal synchronization signal period in which the caption data exists.
The pulse as shown in FIG.
1) occurs. Therefore, a pulse as shown in FIG. 6D is generated from the AND gate (122), and the first and second switches (123) and (1) are generated only during the "H" level period.
24) Close. Then, the VCO (119) shifts the 16-bit shift register (110) in the decoder (107).
Clock signal 32f _H to the would be transmitted only during a period in which the caption data is present, FIG. 6
(F)

On the other hand, the output data of the comparator (115) becomes, for example, as shown in FIG.
24) to the 16-bit shift register (110). Then, the output data of FIG.
The data is taken into the 16-bit shift register (110) according to the clock signal (f). Since the clock signal is applied to the 16-bit shift register (110) only when data is present, the data can be stably taken in without being affected by noise or the like. Further, by applying a gate to the output signal of the comparator (115), that is, output data, it is possible to further increase the stability.

According to the present invention, since the gate pulse is generated based on the synchronizing signal of the video signal on which the caption data is superimposed, it is possible to output the clock signal and the caption data at accurate timing. It is possible. By the way, as described in FIG. 2, since the data itself of the caption data is 2 bytes,
The number of bits of the shift register in the decoder (107) is set to 1
It was 6. However, the three bits of the start bit may be taken into the decoder (107) together. In that case, the number of bits of the shift register is set to 19. As a method of using the start bit, a read start signal of the shift register can be considered.

[0012]

As described above, according to the present invention, caption data of closed caption broadcasting can be stably and reliably held in the shift register. In particular, according to the present invention, since the gate pulse is created directly from the synchronizing signal of the video signal on which the caption data is superimposed, there is an advantage that the clock signal and the data can be accurately extracted.

[Brief description of the drawings]

FIG. 1 is a closed caption broadcast receiving apparatus of the present invention.

FIG. 2 is a waveform chart for explaining closed caption broadcasting.

FIG. 3 is a conventional closed caption broadcast receiving device.

FIG. 4 is a circuit diagram showing one embodiment of a decoder (107) of the device of FIG. 3;

FIG. 5 is a waveform chart for explaining FIG. 4;

FIG. 6 is a waveform diagram for explaining FIG. 1;

[Explanation of symbols]

(110) 16-bit shift register (114) Synchronization separation circuit (115) Comparator ( 116 ) PLL circuit (121) Counter (122) AND gate (123) First switch (124) Second switch

Claims (1)

(57) [Scope of request for utility model registration] 1. A closed caption broadcast receiving apparatus for decoding caption data multiplexed on a television signal and displaying character information on a television screen, comprising: a horizontal synchronization signal and a vertical synchronization signal in the television signal. A synchronization separation circuit for separating a synchronization signal, and a PLL for locking to a horizontal synchronization signal from the synchronization separation circuit
A counter for resetting the output signal of the PLL circuit in response to a vertical synchronization signal from the synchronization separation circuit, and a counter for generating a horizontal scanning period in which caption data exists.
The output signal of the counter and the capacitance during one horizontal scanning period
Output signal of the PLL circuit generated during the option data period.
Gate pulse creation that creates a gate pulse according to the signal
Means, a comparator for extracting caption data in the television signal, and
A shift register that takes in in response to a clock signal from a circuit; and output control means that allows the clock signal applied to the shift register to pass only during a period during which an output gate pulse of the gate pulse generation means is generated. Closed caption broadcast receiver.