JP2540326Y2 - Closed caption broadcast receiver - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a closed caption broadcast receiving apparatus for the deaf in the United States, and more particularly, to a decoder having a shift register for temporarily holding extracted caption data. The present invention relates to a closed caption broadcast receiving device for reducing the number of elements.

[0002]

2. Description of the Related Art Closed caption broadcasting (CLOSED CAP) for displaying conversations, announcements, and the like in a television broadcast program as captions for a deaf person on a television screen.
TION) is taking place in the United States. This is similar to teletext broadcasting in Japan, in which data is transmitted by being superimposed on a vertical retrace period of a video signal. The transmission of the data is a code system, and when displaying characters, a character generator (character generator) is prepared inside the receiver to prepare characters. As a result, it is possible to instantaneously display the code only by sending a code (code) from the broadcast station. The display mode is roughly classified into two types, a text mode (TEXT MODE) and a caption mode (CAPTION MODE). In the text mode, a maximum of 15 lines × 32 characters can be displayed at the center of the television screen, and in the caption mode, the upper and lower sides of the display range, that is, between 1 to 4 columns and 12 to 1 column.
Display is possible only for five columns. The data of the closed caption broadcast is superimposed on the 21st H (H is the horizontal scanning period) of the vertical blanking period, and the enlarged portion is as shown in FIG. Composite signal of 21H eyes shown in FIG. 2 (b) includes a color burst signal of 3.58MH _Z, 5
03KHz _Z run-in clock and caption data.
As shown in (b), a 3-bit start bit, 7-bit data, a parity bit of the data, a 7-bit data,
And a parity bit of the data. Fig. 2 (b)
8-bit data including 1 parity bit (1 byte)
Is transmitted as a unit, and in addition to the above-described character code, a command (command) for determining the position (row and column) and color of the character is transmitted.

[0003] As a receiver of this closed caption broadcast, one as shown in FIG. 3 is conceivable. The television broadcast signal on which the data of the closed caption broadcast is superimposed is received by the antenna (101) of FIG. 3, is tuned by the tuner (102), and is then amplified by the IF (intermediate frequency) amplifier circuit (103). It is detected. The detected video signal is processed by a Y / C (luminance / chroma) processing circuit (104), and an RGB primary color signal is applied to an RGB switching circuit (105).

[0004] Further, from the video signal from the IF amplifier circuit (103), only the caption data is extracted by the extraction circuit (106) and applied to the decoder (107). The decoder (107) performs parity check, display determination, decoding, and the like of caption data. The decoded caption data is applied to a character generator (108) and processed so that a desired character can be displayed at a desired position. Then, according to the processing, R, G, and B primary color signals are generated from the character generator (108), and the output control circuit (10
9) is applied to the RGB switching circuit (105), and the caption characters are displayed on the original television screen.

[0005]

The relationship between the sampling circuit (106) and the decoder (107) in FIG. 3 is shown in detail in FIG. From the sampling circuit (106) in FIG. 4, the data shown in FIG.
A clock signal applied to the 6-bit shift register (110) for taking in the data is also applied as shown in FIG. As is clear from FIG. 5C, the clock signal is applied to the 16-bit shift register (110) only during the period when data exists. Therefore, 1
By counting the number of clocks applied to the 6-bit shift register (110), the completion of counting of the 16-bit shift register (110) can be known. Therefore,
The clock signal is counted by a hexadecimal counter (111), and 1 is output from the latch circuit (112) according to the output signal.
A clock signal for reading is generated in the 6-bit shift register (110). The 16-bit shift register (110) applies data to the latch circuit (112) according to a clock signal from the latch circuit (112),
Latch.

However, the method of FIG. 4 requires a hexadecimal counter (111) and also requires a separate reset pulse to restart the hexadecimal counter (111), which increases the number of elements. There was a problem.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal in a television signal, and a synchronization separation circuit for separating the synchronization signal from the synchronization separation circuit. A PLL circuit for locking to a horizontal synchronization signal,
A counter that is reset in response to a vertical synchronization signal from the synchronization separation circuit and counts an output signal of the PLL circuit; and a gate corresponding to a caption data period in accordance with the output signal of the counter and the output signal of the PLL circuit. Gate pulse generating means for generating a pulse, a comparator for extracting caption data in a television signal, a shift register for capturing caption data from the comparator according to a clock signal from the PLL circuit, and a shift register And an output control means for passing the clock signal applied to only the generation period of the output gate pulse of the gate pulse generation means.

[0008]

According to the present invention, the pulse for extracting the caption data in the extraction circuit (106) is also used as the capture completion signal of the shift register which captures the caption data.

[0009]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.
(113) is a sync separation circuit for separating the horizontal synchronizing signal (H) and the vertical synchronizing signal (V) from the video signal of the IF amplifier (103), and (114) is caption data from the video signal of the IF amplifier (103) (115) is a phase comparator (116), a low-pass filter (117), a VCO (118) and a frequency divider (1).
The PLL circuit (19) counts a signal of 2f _H (f _H is a horizontal synchronizing signal frequency) from the frequency divider (119) as a clock signal, and counts a vertical signal from the synchronizing separation circuit (113). A counter reset in response to a synchronization signal; and (121) an AND gate for generating a gate pulse corresponding to a caption data period in accordance with a divided output of the frequency divider (119) and an output signal of the counter (120). , (122) are 32 from the VCO (118)
first switch for applying a clock signal f _H to the decoder (107), (123) is a second switch for applying the output signal of the comparator (114) to the decoder (107).

In FIG. 1, the same circuit elements as those in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof will be omitted.
VCO of the PLL circuit (115) (118), the center frequency is set to 32f _H. 32f _H is a value for reading caption data, and is a frequency divider (119)
Finally, the frequency is divided to the frequency f _H and the phase comparator (11
6) is applied. On the other hand, in the phase comparator (116),
Since the horizontal synchronization signal is applied from the synchronization separation circuit (113), the PLL circuit ( 115 ) locks to the horizontal synchronization signal. Therefore, the oscillation output signal of the VCO (118) is
This is locked to the phase of the horizontal synchronization signal shown in FIG. The first frequency-divided output signal φ _{1 is} output from the frequency divider (119).
Signal 2f _H is applied to the counter (120) as,
The timing of the pulse extracting the such caption data of FIG. 6 (b) is applied to the AND gate (121) as the second division output signal phi _2. The counter (120)
It is reset according to the vertical synchronization signal from the synchronization separation circuit (113), and starts counting. Then, the counter (120) generates a pulse as shown in FIG. 6C which becomes "H" level during the 21H horizontal synchronization signal period in which the caption data exists. Therefore, AND gate (12
1), a pulse as shown in FIG. 6 (d) is generated, and only during the "H" level period, the first and second switches (12)
2) and (123) are closed. Then, VCO (11
Clock signal 32f _H from 8) to the decoder (107) in a 16-bit shift register (110), would be transmitted only during a period in which the caption data is present, it becomes as shown FIG. 6 (f).

On the other hand, the output data of the comparator (114) becomes, for example, as shown in FIG.
23) to the 16-bit shift register (110). Then, the output data of FIG.
The data is taken into the 16-bit shift register (110) according to the clock signal (f). Since the clock signal is applied to the 16-bit shift register (110) only when data is present, the data can be stably taken in without being affected by noise or the like. Further, by applying a gate to the output signal of the comparator (114), that is, the output data, it is possible to further increase the stability.

As is apparent from the relationship between FIGS. 6E and 6C, the falling of the signal in FIG. 6C can indicate the completion of the data transfer. Therefore, in the present invention, FIG.
The signal of (c) is supplied to the latch circuit (1) in the decoder (107).
12). The latch circuit (112) applies a clock signal to the 16-bit shift register (110) in response to the fall of the signal in FIG.

Therefore, the 16-bit shift register (11
0) can be latched by the latch circuit (112). The output signal of the counter (120) is a signal originally required for generating a gate pulse, and no special circuit is required for a signal indicating the completion of the acquisition.

[0014]

As described above, according to the present invention, a capture completion signal when capturing caption data into the shift register can be used for a pulse for removing caption data, so that special detection means is required. Without
The number of elements can be reduced.

[Brief description of the drawings]

FIG. 1 is a closed caption broadcast receiving apparatus of the present invention.

FIG. 2 is a waveform chart for explaining closed caption broadcasting.

FIG. 3 is a conventional closed caption broadcast receiving device.

FIG. 4 is a circuit diagram showing one embodiment of a decoder (107) of the device of FIG. 3;

FIG. 5 is a waveform chart for explaining FIG. 4;

FIG. 6 is a waveform diagram for explaining FIG. 1;

[Explanation of symbols]

(110) 16-bit shift register (112) Latch circuit (113) Synchronization separation circuit (114) Comparator ( 115 ) PLL circuit (120) Counter (121) AND gate (122) First switch (123) Second switch

Claims (1)

(57) [Scope of request for utility model registration] 1. A closed caption broadcast receiving apparatus for decoding caption data multiplexed on a television signal and displaying character information on a television screen, comprising: a horizontal synchronization signal and a vertical synchronization signal in the television signal. A synchronization separation circuit for separating a synchronization signal, and a PLL for locking to a horizontal synchronization signal from the synchronization separation circuit
A counter for resetting the output signal of the PLL circuit in response to a vertical synchronization signal from the synchronization separation circuit, and a counter for generating a horizontal scanning period in which caption data exists.
The output signal of the counter and the capacitance during one horizontal scanning period
Output signal of the PLL circuit generated during the option data period.
Gate pulse creation that creates a gate pulse according to the signal
Means, a comparator for extracting caption data in the television signal, and
A shift register that captures in response to a clock signal from a circuit; and output control means that allows the clock signal applied to the shift register to pass only during a generation period of an output gate pulse of the gate pulse generation means. A closed caption broadcast receiving device, wherein the signal is a signal indicating that the shift register has been taken in.