JPS6151476B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sampling pulse correction method that is effective for use in systems that receive and reproduce television signals containing character information. In a communication system, when sampling incoming data using sampling pulses,
It is required that the data bits and sampling pulses match in phase with high accuracy. However, the transmitted data is not always kept at a constant phase and amplitude due to disturbances or internal factors. Therefore, a means for accurately extracting data by automatically adjusting the phase of the sampling pulse is desired. This invention was made in view of the above circumstances, and it not only automatically adjusts the phase shift of the sampling clock pulse, but also automatically adjusts the slice level of the data being sent. It is an object of the present invention to provide a sampling pulse correction method for obtaining sampling pulses that can accurately extract data. Embodiments of the present invention will be described below with reference to the drawings. First, a teletext receiving system for a color television receiver to which the present invention is applied will be explained. The format of the television signal used in teletext broadcasting is set as shown in FIG. FIGS. 1a and 1b show vertical blanking period portions of the first field and the next field of a composite video signal, and V is a vertical synchronizing signal. Teletext packets 1 and 2 are set at the rear of this vertical retrace period, for example, at the 20th H (H; one horizontal period) after the previous field ends.
The format of this teletext packet is set as shown in FIG. 1c. H is a horizontal synchronization signal, and 5 is a color burst. The teletext packet 2 is formed by a header section 6 and an information section 7. This teletext packet 2 is shown in more detail in FIG. 1c. That is, the header section 6 contains a clock line (Clockrun in) signal (CRI), a framing code (FC), an identification code (IDC),
It is composed of program codes PC1, PC2, etc. The clock line signal (CRI) is a signal for adjusting the phase of the clock pulses necessary for sampling the data in the teletext packet. A framing code (FC) is a code that indicates the beginning of data. The identification code (IDC) is a code for identifying the display format, transmission signal format, etc., and the program codes PC1 and PC2 are codes indicating the type of text information program. The teletext packets described above are processed, for example, by a system as shown in FIG. 1
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 12. The video-detected composite video signal is input to a waveform shaping circuit 13 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 21 that separates a vertical synchronization signal V and a horizontal synchronization signal H. The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 21 are sent to the vertical position counter 2.
2 is input. This vertical position counter 22 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
By counting the numbers, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is superimposed. The sampling pulse obtained by the vertical position counter 22 is input to the waveform shaping circuit 13. As a result, the teletext packet described in FIG. 1 is extracted from the waveform shaping circuit 13 and its waveform is shaped. The output obtained from this waveform shaping circuit 13 is input to a sampling circuit 14 and also to a clock line signal detection circuit 16. The clock line signal detection circuit 16 is shown in FIG.
The clock line signal (CRI) shown in FIG.
This clock pulse generating circuit 17 has the function of generating continuous clock pulses synchronized with the clock line signal. This clock pulse generation circuit 1
The continuous clock pulses output from 7 are input to the sampling circuit 14 and used as data sampling pulses. In the sampling circuit 14, various types of data as shown in FIG. The output of the sampling circuit 14 is also input to a framing code detection circuit 18.
This framing code detection circuit 18 performs detection by comparing a predetermined framing code and an input code, detects a point where the codes completely match, and detects the beginning of data in the buffer memory. This is what you set. The framing code detection circuit 18 is driven by clock pulses from the horizontal position counter 23, for example. The horizontal position counter 23 is reset by the horizontal synchronization signal H from the synchronization separation circuit 21, and counts the clock pulses from the clock pulse generation circuit 17. This horizontal position counter 2
The count information of 3 is also added to the address circuit 24. Further, this address circuit 24 includes:
The previous vertical sync signal is also input. This address circuit 24 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal. The sample clock in the address circuit uses a gated OSC oscillation clock based on LC resonance. As described above, the buffer memory 15 stores the contents of a teletext packet when it arrives. The data stored in this buffer memory 15 is processed by a microcomputer. Central processing unit (hereinafter referred to as CPU) 30
decodes the data contents of the buffer memory 15. For example, what is the data format?
What the program is like. For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 40. The weather forecast program is specified by the program code shown in FIG. For example, program code
Assuming that the data of PC1 is sending the weather forecast, this program code PC1 is
The calculation is processed by . As a result, if the data in the program code PC1 matches the data designated from the keyboard 40, it is determined that the data in the buffer memory 15 is data for a weather forecast. A command signal for reproducing the weather forecast specified from the keyboard 35 is stored in a random access memory (hereinafter referred to as RAM). The weather forecast pattern data read from the buffer memory 15 is finally written in the pattern memory 33 as character data and symbol data. The color data is stored in color memory 34. The data read from the buffer memory 15 is itself stored in the pattern memory 33 as character data and symbol data, but if the transmission method is a code transmission method, the data read from the buffer memory 15 is decoded and read. Predetermined character data, ie, characters, symbols, solid data, may be read out from the only memory (hereinafter referred to as ROM) and stored in the pattern memory 33 or the like. Therefore, furthermore,
A character ROM 39 is prepared. As mentioned above, characters, symbols, and solid data are stored in the pattern memory 33 based on the data derived from the buffer memory 15.
If a teletext packet in a vertical period is extracted only once, sufficient data for character display cannot be obtained. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 33. When data is stored in the pattern memory 33 and color memory 34, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored. When data stored in the pattern memory 33 and color memory 34 is read out and displayed, the data in the pattern memory 33 is sent to the pattern decoder 35, and the data in the color memory 34 is sent to the color decoder 36 to be converted to DC. is converted to
The output interface 37 synthesizes the signals. Then, it is combined with the composite video signal in a combining circuit 38. The timing of reading data from the pattern memory 33 and color memory 34 is determined by a command signal from the CPU 30. The CPU 30 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 24. When this address data matches the desired display designation data set in the RAM 32, read signals corresponding to these address data are applied to the pattern memory 33 and color memory 34.
The display designation data is included in the program stored in the RAM 32, and various display formats can be set according to changes in the display designation data and program switching. In a system operating as described above, it is important to sample teletext packet data without error in evaluating its performance. Next, the clock pulse generating means according to the present invention will be explained with reference to FIG. In FIG. 3, 52 is an input terminal to which a signal from the video detection stage is applied, and this is connected to one input terminal of the slice circuit 10G.
The output of this slice circuit 10G is the output terminal 53
The signal is input to the sampling circuit 14 via. Therefore, this slice circuit 10G corresponds to the waveform shaping circuit described above. On the other hand, a clock pulse is applied to input terminal 50. This clock pulse is, for example, a carrier wave (CW) synchronized with the color burst created for color reproduction in the main body of the receiver.
is multiplied by 8/5 using a PLL circuit, and is created by an oscillation circuit. This clock pulse is
The signal is corrected by the delay means 10A and output to the sampling pulse output terminal 51. The output sampling pulse of this output terminal 51 is inputted to the sampling circuit 14 as a data sampling pulse. The system shown in FIG. 3 has a function of correcting the data sampling pulse to an appropriate phase and a function of setting the data slice level to an appropriate level. First, this system includes the delay means 10A,
It includes a delay amount control means 10B, a slice level control means 10C, a digital-to-analog converter 10F, and the like. Furthermore, it includes a digital phase detection means 10D for the correction sampling pulse and the clock line signal of the input data, a converter 10E for converting the data output from the digital phase detection means 10D into phase correction information, slice level correction information, etc. . Next, to explain the operation of each part, first, a gate pulse is input to the input terminal 54. This gate pulse sets the operating timing of the system so that it corresponds to the period of the previous clock line signal. This gate pulse is generated during the correction period corresponding to the clock line signal by adding the count information of the previous vertical position counter and horizontal position counter to the logic circuit.
When this system operates, first, as a first process, the amount of delay of the data sampling pulse obtained at the output terminal 51 is set. Furthermore, as a second process, the data slice level in the slice circuit 10G is set. FIG. 4 is a timing chart shown to explain the output information of the digital phase detection means 10D and the converter 10E. FIG. 4a shows, for example, a sampling pulse derived from the output terminal 51, and FIG. 4b shows data output from the slice circuit 10G, which has been waveform-shaped. This case is an example in which the phase of the sampling pulse lags behind the data. The input data is latched into the latch circuit 55 according to the timing of the sampling pulse. Therefore, the output of the latch circuit 55 has a waveform as shown in FIG. 4c. Next, this latch circuit 5
The output of No. 5 is input to a shift register 56 and shifted. In this case, the clock pulse of the shift register 56 is an inverted version of the sampling pulse via the inverter 58, so the output terminals 59, 6 of the shift register 56
The output waveforms of 0 are as shown in FIG. 4e and g, respectively. Furthermore, the slice circuit 10
The output data of G is also input to the shift register 57. This shift register 57 is also driven by a clock pulse obtained by inverting the sampling pulse, and the waveforms at its output terminals 61, 62, and 63 are as shown in FIG. 4d, f, and h, respectively. The outputs d, e, f, g, and h in FIG. 4 are input to the converter 10E. In this converter 10E, arrangements are made in advance by a logic circuit to obtain predetermined output data in accordance with input data. The determined conversion table is as shown below.

[Table] Using this conversion table as a reference, if the phase relationship is as shown in Figure 4, the conversion output information will be D ₁ , D ₂ ,
D ₃ , D ₄ =1,0,0,0. A ₀ , A ₁ , A ₂ ,
A ₃ , A ₄ =0, 1, 1, 0, 0. As described above, if the phase relationship between the data sampling pulse and the data is confirmed, it means that the phase of the sampling pulse is delayed, and therefore it is necessary to control the sampling pulse in a direction to speed up the phase. This control means is the aforementioned delay amount control means 10B, and its operation will be described later. Next, if the phase of the data sampling pulse is ahead of the data, the timing chart will be as shown in FIG. 5A is a data sampling pulse, and FIG. 5B is data output from the slice circuit 10G, which has been waveform-shaped. In the case of such a phase relationship, the latch circuit 55, the output terminals 59, 60 of each shift register 56, 57,
The output waveforms of 61, 62, and 63 are shown in Fig. 5 e, g,
It becomes like d, e, h. As can be seen from the conversion table, the output information of the converter 10E D ₁ , D ₂ ,
D ₃ and D ₄ become 0, 1, 0, 0. As mentioned above, the timing chart in Figure 4 is as follows:
An example is shown in which the phase of the sampling pulse lags behind the data, and the timing chart in FIG. 5 shows an example in which the phase of the sampling pulse leads the data. That is, when the phase of the sampling pulse lags behind the data, the output information of the converter 10E is D ₁ , D ₂ ,
D ₃ , D ₄ = 1, 0, 0, 0 advance D ₁ ,
D ₂ , D ₃ , D ₄ =0, 1, 0, 0. converter 1
The output information D ₁ and D ₂ of 0E becomes control information regarding the amount of delay of the sampling pulse with respect to data.
Further, the output information D ₃ and D ₄ become control information regarding the slice level, which will be described later. Next, the delay amount control means 10B that uses the above information D ₁ and D ₂ will be explained. That is, the above information
Output terminals 54 and 65 that output D ₁ and D ₂ are connected to third input terminals of NAND circuits 71 and 72, respectively. The sampling pulse from the previous output terminal 51 is input to the second input terminals of the NAND circuits 71 and 72. Also, this NAND circuit 7
The previous gate pulse is also applied to the third input terminal 1,72. Therefore, each of the NAND circuits 71 and 72 obtains an output pulse when three inputs are present simultaneously. Output pulses from NAND circuits 71 and 72 are input to counters 73 and 74, respectively. The NAND circuits 71 and 72 can obtain output pulses from either one, and the counters 73 and 74
obtains an output when a plurality of, for example four, consecutive pulses are applied to each input. Also, when there is an output from the AND circuit 71, the counter 73
The counter operation progresses, but in this case, the OR circuit 76
The counter 74 is cleared via the . Conversely, when there is an output from the AND circuit 72, the counting operation of the counter 74 advances, but in this case, the counter 73 is cleared via the OR circuit 75. The counter 73 is also cleared via the OR circuit 75 by its own output pulse (up-count command signal). Furthermore, the counter 74 is also cleared via the OR circuit 76 by its own output pulse (down count command signal). The outputs of the counters 73 and 74 are input to an up-count command signal input terminal and a down-count command signal input terminal of an up-down counter 80, respectively. When a gate pulse corresponding to the period of the clock line signal is applied to the input terminal 54, one of the NAND circuits 71 and 72 derives a data sampling pulse according to the contents of the information _D1 and _D2 . . In this case, the information D ₁ and D ₂ may repeat 0, 1, 1, 0 every vertical period. Further, due to an error in the information D ₁ and D ₂ , 1, 0, 0, 1 may be repeated momentarily. If the count value of the up-down counter 80 is varied in response to such an uncertain situation in the information D ₁ and D ₂ , the data sampling pulse may cause phase distortion or noise. There is. Therefore, according to the circuit above,
If there is an unnecessary change in information D ₁ and D ₂ ,
This is designed to be absorbed by counters 73 and 74. Next, the use of the output information from the up-down counter 80 will be explained. This output information is
It is used as control information for selection circuits 85 and 86. That is, the output terminals 81, 82, 83, 84 of the up-down counter 80 are connected to the selection circuits 85, 8
6 control terminals 81a, 82a, 83a, and 84a. In this case, the most significant bit output terminal 84a is connected directly to the control terminal of the selection circuit 85 and to the control terminal of the selection circuit 86 via an inverter 87. Therefore, when the output terminal 84a of the most significant bit is "0", the selection circuit 85 is in the operating mode and the selection circuit 86 is in the non-operating mode. Further, when the output terminal 84a of the most significant bit is "1", the selection circuit 85 is in the non-operating mode, and the selecting circuit 86 is in the operating mode. Based on the control information, the selection circuit 85 selects one of the pulses at the input terminals of the AND circuits 88 to 95 and outputs it to the output terminal 85a. The selection circuit 86 also selects one of the pulses at the input terminals of the AND circuits 96 to 102 and the pulse at the output terminal of the AND circuit 102 based on the control information, and outputs the selected pulse to the output terminal 86a. Selection circuit 85
Alternatively, the corrected sampling pulse derived from 86 is derived to output terminal 51 through NAND circuit 104 and exclusive OR circuit 105. In addition, the exclusive OR circuit 105 includes
The output of latch circuit 107 is also added. this is,
If the up-down counter 80 overflows, this means that the data and sampling pulse phases are significantly different, so the NAND circuit 10
6. This is to invert the sampling pulse to the opposite phase through the latch circuit 107 to speed up the subsequent pull-in (delay amount matching). As described above, the delay amount of the corrected sampling pulse is determined based on the information from the up-down counter 80 and is output. AND circuit 88,
90,92,94,96,98,100,10
2, 88, 89, 90, 91, 92, 93, 94
...Each signal waveform at the input end of 102 is shown in Fig. 6 a to g...
h, and one of these is selected. FIG. 6i shows an example in which the signal in FIG. 6f is selected and derived and appears at the output terminal 51. Next, a control system regarding the data slice level will be explained. The basic information regarding the slice level is the output information D ₃ and D ₄ of the converter 10E. That is, the output terminal 6 that derives the output information D ₃ and D ₄
6 and 67 are connected to second input terminals of NAND circuits 110 and 111. This NAND circuit 11
A data sampling pulse obtained from the output terminal 51 is applied to the first input terminal at 0,111. Further, the aforementioned gate pulse is applied to the third input terminals of the NAND circuits 110 and 111. Furthermore, the overflow output of the up-down counter 118 when counting up is applied to the fourth input terminal of the NAND circuit 110. The slice level control means 10C also obtains the same operation as the delay amount control means 10B, and the NAND circuits 110 and 111 correspond to the NAND circuits 71 and 72, and the OR circuits 114 and 1
15 corresponds to the previous OR circuits 75 and 76, and counters 112 and 113 correspond to the previous counters 73 and 74. Up-down counter 117, 118
are arranged in two columns in tandem, and this is because the number of bits is increased in order to make the variable range large or fine. The output information of the up-down counters 117 and 118 is input to the digital-to-analog converter 10F. The analog output thereof is input to the data slicing circuit 10G as a signal for setting a slice level. Next, we will discuss the necessity of inputting data into the slicing circuit and setting the slicing level to an appropriate level. In other words, if the data input to the input terminal 52 has a waveform as shown in _FIG . % square wave signal. If this data is sampled with a clock pulse of twice the frequency (as shown in Figure c), an accurate digitally converted code of the data can be obtained. However, when the slice level changes to _S2 as shown in the figure, the output data of the slice circuit 10G becomes as shown in FIG. 7d. This is the data sampling pulse (e in the same figure).
) shown in the figure. An ambiguous part occurs in the code at the position indicated by , and accurate sampling cannot be obtained. Therefore, it is necessary to set the slice level to an appropriate level. Next, the control operation when the slice level is too high will be explained with reference to the signal waveform of FIG. 8. FIG. 8a shows a sampling pulse, and FIG. 8b shows data output from the slice circuit 10G. In this data, the pulse duty was less than 50% because the slice level was high. Further, c in the figure is the output of the latch circuit 55, and the data sampling state is unstable.
It is "0". As a result, the signal waveforms at the input terminals 59 to 63 of the converter 10E are as shown in FIG.
It becomes like g, d, e, h. When such a signal is input, the outputs D ₁ to _{D 4} of the converter 10E are D ₁ , D ₂ , D ₃ , D ₄ = as shown in FIG. 8 i and l.
It becomes 0, 0, 0, 1. As a result, the basic information D ₃ and D ₄ regarding the slice level have become 0 and 1, so the count value of the counter 113 is varied, and the output information of the up-down counters 117 and 118 is varied. This output information changes in the direction of lowering the slice level, and the slice circuit 10G
The slice level can be set to an appropriate value. According to the above-described data sampling method according to the present invention, especially when correcting the data sampling pulse, it is provided with a delay amount and slice level correction function, and the data sampling pulse can be made accurate. In this invention, the digital phase detection means 1
At 0D, a phase comparison is made between the corrected sampling pulse and the input data, and information corresponding to the phase error is obtained at output terminals 59 to 63 according to the phase error. In this case, the frequency of the correction sampling pulse is 2 compared to the frequency of the set input data.
It's double. Next, information from the digital phase detection means 10D is input to the converter 10E. Information D ₁ and D ₂ for adjusting the phase of the corrected sampling pulse and information D ₃ and D ₄ for adjusting the slice level of the data are stored in advance in a conversion table (table).
is obtained from the set converter 10E. In other words, the converter 10E allocates the objects to be controlled according to the input information. Conversion table (table)
If the phase between the correction sampling pulse and the data is small, the information D ₁ or D ₂ is mainly used to control the delay amount, and if the phase is large, the information D ₃ is used to control the slice level.
Or it is set to vary _D4 . In this way, the digital phase detection means 10D and the converter 10E can perform phase comparison between the corrected sampling pulse and data, and obtain delay (phase) amount control information and data slice level control information of the corrected sampling pulse. can. Next, information D ₁ to _{D 4} output from the converter 10E
When determining the correction amount based on Also, NAND circuit 110,
111, OR circuit 114, 115, counter 11
2,113, up-down counter 117,11
8 is used. The counters 73 and 74 are set to output an up-count or down-count command signal once only when the count value reaches a certain value, for example, 4. In other words, the combination of a counter and an up-down counter has the advantage that the control range for delay can be varied in very fine steps and resolution can be improved. Furthermore, by increasing the number of bits in the up-down counter, a wide control range can be set. Furthermore, by the operation of counters 73 and 74, a small number of pulse inputs (4
Since no up-count or down-count command signals are issued up to 1), unnecessary malfunctions can be eliminated. Regarding the prevention of malfunction,
When a command signal is output from one counter to the up-down counter, the other counter is cleared through the OR circuit, so an up-down count command signal that does not require such an operation is output. It can help prevent this. As mentioned above, the present invention not only automatically adjusts the phase shift of the sampling clock pulse, but also automatically adjusts the slice level of the data being sent, thereby creating a sampling pulse that accurately extracts data. In particular, it is possible to provide a sampling pulse correction method that can prevent unnecessary operations in the correction operation and contribute to obtaining accurate sampling pulses.

[Brief explanation of the drawing]

Figures 1 a to d are diagrams explaining the format of teletext packets used in teletext broadcasting, Figure 2 is a diagram showing a system for processing teletext packets, and Figure 3 is an embodiment of the present invention. 4a-l and 5a-l are time charts shown to explain the operation of the digital phase detection means and converter, and FIGS. 6a-i are diagrams showing the configuration of the delay means. The time charts shown in Figures 7a to 7e to explain the operation are signal waveform diagrams explaining the necessity of setting the slice level for data, and Figures 8a to l are the signal waveform diagrams shown when the slice level is high. This is a time chart shown to explain the operation of the digital phase detection means and converter. 10A...Delay means, 10B...Delay amount control means, 10C...Slice level control means, 10D
...Digital phase detection means, 10E...Converter,
10F...Digital analog converter, 10G...
Slice circuit, 71, 72, 110, 111...
NAND circuit, 75, 76, 114, 115... OR circuit, 73, 74, 112, 113... counter, 80, 117, 118... up/down counter.

Claims (1)

[Claims] 1. A slice circuit in which data to be extracted is input to one input terminal, and the output of a digital-to-analog converter that sets an analog reference voltage according to digital control data is applied to the other input terminal; In order to sample the data from an oscillator, a sampling pulse having a frequency twice that of the data is inputted, and this sampling pulse is delayed to different phases at various points, and each delayed pulse is applied to each corresponding input terminal of the selection circuit. Based on the control information input and applied to the control terminal of the selection circuit,
a delay correction means for deriving one phase of the delayed sampling pulse and using it as a corrected sampling pulse; and a delay correction means for inputting the data derived from the slice circuit and the corrected sampling pulse, and determining the phase relationship between both inputs. a shift register for deriving information indicative of at least 5 bits of information;
This information is converted based on a preset conversion table to provide 2-bit information for controlling the delay amount of the sampling pulse and 2-bit information for controlling the slice level of the data. Means including a converter for outputting, information for controlling the delay amount, and a gate pulse indicating the delay amount or slice level correction period are input, and depending on the content of the information for controlling the delay amount A first logic circuit that obtains a logic output of a predetermined level at a first or second output terminal, and a clock pulse is counted by a predetermined logic output of the first and second output terminals of the first logic circuit. first and second counters that each derive an output when the count reaches a predetermined count value, and a first counter that clears the second counter in response to a predetermined logic output from the first output terminal. a second OR circuit that clears the first counter according to a predetermined logical output from the OR circuit and the second output terminal; The output of the counter is applied to the down count command signal input terminal,
A first up-down counter that applies a count output to a control terminal of the selection circuit, and a gate pulse that inputs information for controlling the slice level and a delay amount or a slice level correction period, and controls the slice level. Depending on the content of the information for control, a second logic circuit that obtains a logic output at the first or second output terminal, and a predetermined logic output at the first and second output terminals of this second logic circuit. third and fourth counters that count clock pulses and derive outputs when a predetermined count value is reached; and in response to a predetermined logic output from the first output terminal of the second logic circuit. a third OR circuit that clears the fourth counter; a fourth OR circuit that clears the third counter in response to a predetermined logical output from the second output terminal; and an output of the third counter. is an up-count command signal input terminal, the output of a fourth counter is applied to a down-count command signal input terminal, and a second up-down counter outputs the count output as digital control data of the digital-to-analog converter. A sampling pulse correction method characterized by: