JPS6258598B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sampling pulse correction method that is effective for use in systems that receive and reproduce television signals containing character information. In a communication system, when sampling incoming data using sampling pulses,
It is required that the data bits and sampling pulses match in phase with high precision. However, the transmitted data is not always kept at a constant phase and amplitude due to disturbances or internal factors. Therefore, a means for accurately extracting data by automatically adjusting the phase of the sampling pulse is desired. This invention was made in view of the above circumstances, and it not only automatically adjusts the phase of the clock pulse for sampling, but also automatically adjusts the slice level of the data being sent. An object of the present invention is to provide a sampling pulse correction method that obtains a sampling pulse that can accurately extract the . Embodiments of the present invention will be described below with reference to the drawings. First, a teletext receiving system for a color television receiver to which the present invention is applied will be explained. The format of the television signal used in teletext broadcasting is set as shown in FIG. 1a and 1b show the vertical blanking period portions of the first field and the next field of a composite video signal, where V is a vertical synchronizing signal. Teletext packets 1 and 2 are set at the rear of this vertical retrace period, for example, at the 20th H (H; one horizontal period) after the end of the previous field. The format of this teletext packet is set as shown in Figure 1c. H is a horizontal synchronization signal, and 5 is a color burst.
The teletext packet 2 has a header section 6 and an information section 7.
It is formed by. This teletext packet 2 is shown in more detail in FIG. 1d. That is, the header section 6 includes a clock run in signal CRI, a framing code FC, an identification code IDC, program codes PC1, PC2, and the like. The clock run-in signal CRI is a signal for adjusting the phase of the clock pulses necessary for sampling the data in this teletext packet. Fleming code FC is a code that indicates the beginning of data. Identification eye code IDC is a code for identifying display format, transmission signal format, etc. Programs PC1 and PC2 are
This is a code indicating the type of text information program. The teletext packets described above are processed, for example, by a system as shown in FIG. 1
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 12. The video-detected composite video signal is input to a waveform shaping circuit 13 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 21 that separates a vertical synchronization signal V and a horizontal synchronization signal H. The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 21 are sent to the vertical position counter 2.
2 is input. This vertical position counter 22 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
By counting the numbers, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is superimposed. The sampling pulse obtained by the vertical position counter 22 is input to the waveform shaping circuit 13. As a result, the waveform shaping circuit 13 extracts the teletext packet described in FIG. 1 and shapes its waveform. The output obtained from this waveform shaping circuit 13 is input to a sampling circuit 14 and also to a clock run-in signal detection circuit 16. The clock run-in signal detection circuit 16 extracts the clock run-in signal CRI shown in FIG.
This clock pulse generating circuit 17 has a function of generating continuous clock pulses in synchronization with the clock run-in signal. Continuous clock pulses output from the clock pulse generating circuit 17 are input to the sampling circuit 14 and used as data sampling pulses. In the sampling circuit 14, various types of data as shown in FIG. The output of the sampling circuit 14 is also input to a framing code detection circuit 18.
This framing code detection circuit 18 performs detection by comparing a predetermined framing code and an input code, detects a point where the codes completely match, and detects the beginning of data in the buffer memory. This is what you set. Framing code detection circuit 18 is driven by clock pulses from horizontal position counter 23, for example. The horizontal position counter 23 is reset by the horizontal synchronization signal H from the synchronization separation circuit 21, and counts the clock pulses from the clock pulse generation circuit 17. This horizontal position counter 2
The count information of 3 is also added to the address circuit 24. Further, this address circuit 24 includes:
The previous vertical synchronization signal is also input. This address circuit 24 can generate address data regarding the horizontal direction of the image obtained by the currently input composite video signal. here,
Gated by LC resonance as basic clock
Uses the OSC oscillation clock. As described above, the buffer memory 15 stores the contents of a teletext packet when it arrives. The data stored in this buffer memory 15 is processed by a microcomputer. Central processing unit (hereinafter referred to as CPU) 30
decodes the data contents of the buffer memory 15. For example, what is the data format?
What the program is like. For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 40. The weather forecast program is specified by the program code shown in FIG. For example, the program code
Assuming that the data of PC1 is sending the weather forecast, this program code PC1 is
The calculation is processed in . As a result, if the data in the program code PC1 matches the data designated from the keyboard 40, it is determined that the data in the buffer memory 15 is data for a weather forecast. A command signal for reproducing a weather forecast specified from the keyboard 40 is stored in a random access memory 32 (hereinafter referred to as RAM). The weather forecast pattern data read from the buffer memory 15 is finally stored in the pattern memory 33 as character data and symbol data. The color data is stored in color memory 34. The data read from the buffer memory 15 is itself stored in the pattern memory 33 as character data or symbol data, but if the transmission method is a code transmission method, the data read from the buffer memory 15 is decoded and read. Predetermined character data, that is, characters, symbols, and graphic data may be read out from the only memory 31 (hereinafter referred to as ROM) and stored in the pattern memory 33 or the like. Therefore, a character ROM 39 is also provided. As mentioned above, character, symbol, and graphic data are stored in the pattern memory 33 based on the data derived from the buffer memory 15.
If a teletext packet in a vertical period is extracted only once, sufficient data for character display cannot be obtained. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 33. When data is stored in the pattern memory 33 and color memory 34, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored. When data stored in the pattern memory 33 and color memory 34 is read out and displayed, the data in the pattern memory 33 is sent to the pattern decoder 35, and the data in the color memory 34 is sent to the color decoder 36 to be converted to DC. is converted to
The output interface 37 synthesizes the signals. Then, it is combined with the composite video signal in a combining circuit 38. The data read timing of the pattern memory 33 and color memory 34 is based on a command signal from the CPU 30. The CPU 30 is a constant address circuit 2
The address data (corresponding to the current screen beam irradiation position) input from 4 is connected. When this address data matches the desired display designation data set in the RAM 32, read signals corresponding to these address data are applied to the pattern memory 33 and color memory 34. The display instruction data is included in a program stored in the RAM 32, and various display formats can be set according to changes in the display instruction data and program switching. In a system operating as described above, it is important to sample teletext packet data without error in evaluating its performance. Next, the clock pulse generating means according to the present invention will be explained with reference to FIG. In FIG. 3, 52 is an input terminal to which a signal from the video detection stage is applied, and this is connected to one input terminal of the slice circuit 10G.
The output of this slice circuit 10G is the output terminal 53
The signal is input to the sampling circuit 14 via. Therefore, this slice circuit 10G corresponds to the waveform shaping circuit 13 described above. On the other hand, a clock pulse is applied to input terminal 50. This clock pulse is 8/5 _SC ( _SC :
For example, it is a CW wave (carrier wave wave) synchronized with the color burst generated for color reproduction in the receiver body by oscillating a clock pulse and outputting it.
is multiplied by 8/5 using a PLL circuit, and is created by an oscillation circuit. This clock pulse is corrected by delay means 10A and output to sampling pulse output terminal 51. The output sampling pulse of this output terminal 51 is inputted to the sampling circuit 14 as a data sampling pulse. The system shown in FIG. 3 has a function of correcting the data sampling pulse to an appropriate phase and a function of setting the data slice level to an appropriate level. First, this system includes the delay means 10A,
It includes a delay amount control means 10B, a slice level control means 10C, a digital-to-analog converter 10F, and the like. Furthermore, digital phase detection means 10D for a clock run-in signal of the corrected sampling pulse and input data;
It has a converter 10E, etc. that converts data output from the converter into phase correction information and slice level correction information. Next, to explain the operation of each part, first, a gate pulse is input to the input terminal 54. This gate pulse sets the operating timing of this system so that it operates in accordance with the period of the previous clock run-in signal. This gate pulse is generated during the correction period corresponding to the clock run-in signal by adding the count information of the vertical position counter 22 and horizontal position counter 23 to the logic circuit. When this system operates, first, as a first process, the amount of extension of the data sampling pulse obtained at the output terminal 51 is set. Furthermore, as a second process, the data slice level in the slice circuit 10G is set. FIG. 4 is a timing chart shown to explain the output information of the digital phase detection means 10D and the converter 10E. FIG. 4a shows, for example, a sampling pulse derived from the output terminal 51, and FIG. 4b shows data output from the slice circuit 10G, which has been waveform-shaped. This case is an example in which the phase of the sampling pulse lags behind the data. The input data is latched into the latch circuit 55 according to the timing of the sampling pulse. Therefore, the output of the latch circuit 55 has a waveform as shown in FIG. 4c. Next, this latch circuit 5
The output of No. 5 is input to a shift register 56 and shifted. In this case, the clock pulse of the shift register 56 is an inverted version of the sampling pulse via the inverter 58, so the output terminals 59, 6 of the shift register 56
The output waveforms of 0 are as shown in FIG. 4e and g, respectively. Furthermore, the slice circuit 10
The output data of G is also input to the shift register 57. This shift register 57 is also driven by a clock pulse obtained by inverting the sampling pulse, and its outputs 61, 62, and 63 have waveforms as shown in FIG. 4d, f, and h, respectively. The outputs d, e, f, g, and h in FIG. 4 are input to the converter 10E. In this converter 10E, arrangements are made in advance by a logic circuit to obtain predetermined output data in accordance with input data. This determined conversion table is as shown below.

【table】

[Table] Referring to this conversion table, if the phase relationship is as shown in Figure 4, the conversion output information is (D ₁ , D ₂ ,
D ₃ , D ₄ )=(1, 0, 0, 0). (A ₀ , A ₁ ,
A ₂ , A ₃ , A ₄ )=(0, 1, 1, 0, 0).
As described above, if the phase relationship between the data sampling pulse and the data is confirmed, it means that the phase of the sampling pulse is delayed, and therefore it is necessary to control the sampling pulse in a direction to speed up the phase. This control means is similar to the delay amount control means 10 described above.
B, and this operation will be described later. Next, if the phase of the data sampling pulse is ahead of the data, the timing chart will be as shown in FIG. 5A is a data sampling pulse, and FIG. 5B is data output from the slice circuit 10G, which has been waveform-shaped. In the case of such a phase relationship, the latch circuit 55, the output terminals 59, 60 of each shift register 56, 57,
The output waveforms of 61, 62, and 63 are shown in Fig. 5 e, g,
It becomes like d, f, h. As can be seen from the conversion table, the output information (D ₁ , D ₂ ,
D ₃ , D ₄ ) becomes (0, 1, 0, 0). As mentioned above, the timing chart in Figure 4 is as follows:
An example is shown in which the phase of the sampling pulse lags behind the data, and the timing chart in FIG. 5 shows an example in which the phase of the sampling pulse leads the data. That is, when the phase of the sampling pulse lags behind the data, the output information of the converter 10E is (D ₁ , D ₂ ,
If D ₃ , D ₄ )=(1, 0, 0, 0), then (D ₁ , D ₂ , D ₃ , D ₄ )=(0, 1, 0, 0).
The output information D ₁ and D ₂ of the converter 10E becomes control information regarding the amount of delay of the sampling pulse with respect to data. Further, the output information D ₃ and D ₄ become control information regarding the slice level, which will be described later. Next, the delay amount control means 10B that uses the data D ₁ and D ₂ will be explained. That is, the above information
Output terminals 64 and 65 that output D ₁ and D ₂ are connected to third input terminals of NAND circuits 71 and 72, respectively. The sampling pulse from the previous output terminal 51 is input to the second input terminals of the NAND circuits 71 and 72. Also, this NAND circuit 7
The previous gate pulse is also applied to the third input terminal 1,72. Therefore, the NAND circuit 71,7
2 each obtain an output pulse when three inputs are present simultaneously. Output pulses from NAND circuits 71 and 72 are input to counters 73 and 74, respectively. The NAND circuits 71 and 72 can obtain output pulses from either one, and the counter circuits 73 and 7
4, the count values thereof are compared by a comparator 75. When the count value of the counter circuit 73 is large, the comparator 75 outputs the output from the output terminal 7.
If the count value of the counter circuit 74 is large, "0" is output to the output terminal 76 and "1" is output to the output terminal 77. Output terminals 76, 7 of comparator 75
7 is connected to each second input terminal of AND circuits 78 and 79. On the other hand, the timing pulse P ₁ is applied to the first input terminals of the AND circuits 78 and 79. This timing pulse is applied to the comparator 75
It is added after the comparison results are obtained, for example when the framing signal starts. As a result, the AND circuit 78 or 79 outputs an up-count or down-count command signal to the up-down counter 80.
As a result, the output information of the up-down counter 80 is varied, and this is input to the delay amount correction means 10A. When a gate pulse is applied to the period input terminal 54 of the clock run-in signal, the information at that time is
Depending on D ₁ and D ₂ , counter 73 or 74 will count data sampling pulses. Then, the comparison operation of the comparator 75 is obtained, and the output data of the up-down counter 80 is determined at the start of the framing signal. The contents of the counters 73 and 74 are cleared by applying a timing pulse _P2 around the end of the teletext packet period, in preparation for the next operation. Next, the use of the output information from the up-down counter 80 will be explained. This output information is
It is used as control information for selection circuits 85 and 86. That is, the output terminals 81, 82, 83, 84 of the up-down counter 80 are connected to the selection circuits 85, 8
6 control terminals 81a, 82a, 83a, and 84a. In this case, the most significant bit output terminal 84a is connected directly to the control terminal of the selection circuit 85 and to the control terminal of the selection circuit 86 via an inverter 87. Therefore, when the output terminal 84a of the most significant bit is "0", the selection circuit 85 is in the operating mode and the selection circuit 86 is in the non-operating mode. Further, when the output terminal 84a of the most significant bit is "1", the selection circuit 85 is in the non-operating mode, and the selecting circuit 86 is in the operating mode. Based on the control information, the selection circuit 85 selects one of the pulses at the input terminals of the AND circuits 88 to 95 and outputs it to the output terminal 85a. The selection circuit 86 also selects one of the pulses at the input terminals of the AND circuits 96 to 102 and the pulse at the output terminal of the AND circuit 102 based on the control information, and outputs the selected pulse to the output terminal 86a. Selection circuit 85
Alternatively, the corrected sampling pulse derived from 86 is derived to output terminal 51 through NAND circuit 104 and exclusive OR circuit 105. Further, the output of the latch circuit 107 is also added to the exclusive OR circuit 105. This is because when the up-down counter 80 overflows, the data and sampling pulse phases are greatly different, so the sampling pulse is inverted to the opposite phase through the NAND circuit 106 and the latch circuit 107, and the required phase is inverted. This is to reduce the number of delay elements (AND circuits 88 to 102) by half. As described above, the delay amount of the corrected sampling pulse is determined based on the information from the up-down counter 80 and is output. AND circuit 88,
The signal waveforms at the input terminals 89, 90, 91, 92, 93, 94, . . . , 102 are as shown in FIG. FIG. 6i shows an example in which the signal in FIG. 6f is selected and derived and appears at the output terminal 51. Next, a control system regarding the data slice level will be explained. The basic information regarding the slice level is the output information (D ₃ , D ₄ ) of the converter 10E. That is, the output terminals 66 and 67 that derive the output information (D ₃ , D ₄ ) are the second terminals of the NAND circuits 110 and 111.
connected to the input terminal. This NAND circuit 11
A data sampling pulse obtained from the output terminal 51 is applied to the first input terminal at 0,111. Further, the aforementioned gate pulse is applied to the third input terminals of the NAND circuits 110 and 111. Furthermore, the overflow output of the up-down counter 118 when counting up is applied to the fourth input terminal of the NAND circuit 110. Furthermore, the overflow output of the up-down counter 118 when counting down is applied to the fourth input terminal of the NAND circuit 111. The NAND circuits 110, 111, counters 112, 113, comparator 114, AND circuits 115, 116, up/down counters 117, 118, etc. obtain the same operation as the correction amount control means 10B for controlling the delay amount described above. In this case, in order to increase the variable range (output data), up-down counters 117 and 118 are connected in cascade. The output information of the up-down counters 117 and 118 is input to the digital-to-analog converter 10F. The analog output thereof is input to the data slicing circuit 10G as a signal for setting a slice level. Next, we will discuss the necessity of inputting data into the slicing circuit and setting the slicing level to an appropriate level. In other words, if the data input to the input terminal 52 has a waveform as shown in _FIG .
% square wave signal. This data has a frequency of 2
By sampling with twice the clock pulses (as shown in Figure 3c), an accurate digitally converted code of the data can be obtained. However, when the slice level changes to _S2 as shown in the figure, slice circuit 1
The output data of 0G is as shown in FIG. 7d. If this is sampled with a data sampling pulse (shown in e of the same figure), the ? An ambiguous part occurs in the code at the position indicated by , and accurate sampling cannot be obtained. Therefore, it is necessary to set the slice level to an appropriate level. Next, the control operation when the slice level is too high will be explained with reference to the signal waveform of FIG. 8. FIG. 8a shows a sampling pulse, and FIG. 8b shows data output from the slice circuit 10G. In this data, the pulse duty was less than 50% because the slice level was high. Further, c in the figure is the output of the latch circuit 55, which is "0" because the data sampling state is unstable. As a result, the signal waveforms at the input terminals 59 to 63 of the converter 10E are as shown in FIG.
It becomes like g, d, f, h. When such a signal is input, the output (D ₁ to D ₄ ) of the converter 10E is
As shown in Figure 8 i-l, (D ₁ , D ₂ , D ₃ , D ₄ )
= (0, 0, 0, 1). As a result, the basic information (D ₃ , D ₄ ) regarding the slice level is (0,
1), the count value of the counter 113 is changed, and the up-down counter 117,
The output information of 118 is varied. This output information changes in the direction of lowering the slice level, making it possible to set the slice level in the slice circuit 10G to an appropriate level. According to the above-described data sampling method according to the present invention, especially when correcting the data sampling pulse, it is provided with a delay amount and slice level correction function, and data sampling can be made accurate. In this invention, the digital phase detection stage 10
At D, the phase of the corrected sampling pulse and the input data is compared, and information corresponding to the phase error is obtained at output terminals 59 to 63 according to the phase error. In this case, the frequency of the correction sampling pulse is 2 compared to the frequency of the set input data.
It's double. Information from the digital phase detection stage 10D is then input to a converter 10E. This provides information for adjusting the phase of the correction sampling pulse.
D ₁ , D ₂ , and information D ₃ and D ₄ for adjusting the slice level of the data are obtained from the converter 10E in which a conversion table (table) is set in advance. In other words,
The converter 10E will allocate the objects to be controlled according to the input information. The conversion table (table) is
If the phase between the correction sampling pulse and the data is small, the information D ₁ or D ₂ is varied mainly to control the amount of delay, and if the phase is large, the information D ₃ or D 2 is varied to control the slice level.
It is set to vary D ₄ . In this way, the digital phase detection means 10D and the converter 10E compare the phases of the corrected sampling pulse and the data, and obtain the delay (phase) amount control information of the corrected sampling pulse and the slice level control information of the data. be able to. Next, information D ₁ to _{D 4} output from the converter 10E
When determining the correction amount based on 112, 11
3. Comparator 114, AND circuit 115,1
16, up-down counters 117 and 118 are used. This has the advantage of improving sampling accuracy since the control range can be varied in very fine steps. Also, by increasing the number of bits (up-down counter), it means that a wide control range can be set. Therefore, optimal phase matching between the sampling pulse and the data can be obtained even more accurately, contributing to stable and accurate sampling of the data. As mentioned above, this invention not only automatically adjusts the phase of the sampling clock pulse, but also automatically adjusts the slice level of the data being sent, making it possible to extract data accurately. It is possible to provide a sampling pulse correction method that can perform the following steps.

[Brief explanation of the drawing]

Figures 1 a to d are diagrams explaining the format of teletext packets used in teletext broadcasting, Figure 2 is a diagram showing a system for processing teletext packets, and Figure 3 is an embodiment of the present invention. 4a-l and 5a-l are time charts shown to explain the operation of the digital phase detection means and converter, and FIGS. 6a-i are diagrams showing the configuration of the delay means. The time charts shown in Figures 7a to 7e to explain the operation are signal waveform diagrams explaining the necessity of setting the slice level for data, and Figures 8a to l are the signal waveform diagrams shown when the slice level is high. This is a time chart shown to explain the operation of the digital phase detection means and converter. 10A...Delay means, 10B...Delay amount control means, 10C...Slice level control means, 10D
...Digital phase detection means, 10E...Converter,
10F...Digital analog converter, 10G...
Slice circuit, 71, 72, 110, 111...
NAND circuit, 73, 74, 112, 113... Counter, 75, 114... Comparator, 78,
79,115,116...AND circuit, 80,1
17,118...Up-down counter.

Claims (1)

[Claims] 1. A slicing means for slicing data to be extracted according to a set slicing level, and a sampling clock having the same frequency as the sampling clock for sampling the data sliced by the slicing means, respectively. pulse train generating means for generating pulse trains having mutually different phases; and a pulse train selection for selecting and outputting one of the pulse trains generated from the pulse train generating means as the sampling pulse according to set pulse selection data. sampling means for sampling at least one cycle period of the sliced data with a pulse having a frequency at least twice that of the sampling pulse output from the pulse train selection means, and determining the phase of the sampling pulse and the state of the slice level. a state detection means for detecting; and a correction for outputting phase correction data and level correction data for setting the phase of the sampling pulse and the slice level to appropriate phases and levels based on the detection result of the state detection means. a data output means, which counts phase correction data output from the correction data output means in a predetermined period according to the type of the phase correction data, and selects the pulse selection data based on the type of phase correction data having a large count value; phase correction means for correcting and setting it in the pulse train selection means; and counting level correction data output from the correction data output means for a predetermined period according to the type of the level correction data, and selecting the level of the type with the largest count value. A sampling pulse correction method comprising: a level correction means for correcting the slice data based on correction data and setting the corrected slice data in the slice means.