JPS5850775U - receiving device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

, Figures 1a and 1b are explanatory diagrams of the structure of a character signal, Figure 2 is a block diagram of a conventional receiving device, Figure 3 and the following drawings show an embodiment of the receiving device of this invention, and Figure 3 is a block diagram of a conventional receiving device. Block diagram, Figure 4 is a detailed block diagram of a part of Figure 3, Figure 5a
” f is a timing chart for explaining the operation of FIGS. 3 and 4. B: reproduction clock circuit, D: framing code detection circuit, F: Input buffer memory, G... Data processing circuit, ■...
...Counting circuit, J...Nuttogate.

Claims (1)

[Scope of utility model registration request] In a receiving device that receives a clock run-in signal and a framing code that have been sent out, and an information code that has been sent out subsequent to the framing code, the clock run-in signal is used to control the sample timing of the information code. a regenerated clock circuit that forms a regenerated clock signal; a framing code detection circuit that uses the framing code to form a detection pulse signal for controlling the detection start timing of the information code; and a framing code detection circuit that counts the regenerated clock signal and generates the detection pulse signal. a counting circuit that outputs a counting pulse signal at the timing when the detection pulse signal and the counting pulse signal are formed; A receiving device comprising: a write address generation circuit that outputs an address signal for controlling writing of an information code memory circuit; and a data processing circuit that processes the information code via the memory circuit. −