JP4824422B2 - Control device, image processing system, and data transfer path switching method - Google Patents

Description

The present invention relates to a control device, an image processing system, and a data transfer path switching method.

  In general, in an image processing system such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a parallel bus such as a PCI bus is used as an interface between devices.

  Here, FIG. 22 is a block diagram showing an example of a controller configuration of a conventional image processing system. As shown in FIG. 22, the controller 100 of the image processing system continuously manages a large amount of data that flows simultaneously between the devices with respect to the interconnection of the input / output systems of the image data between the devices, as well as a scanner and a printer. Each device is controlled so as to fulfill the functions of the image input / output apparatus 200. And when high-speed processing is required, in order to adapt to high-speed processing such as CPU (Central Processing Unit) 101 and main memory 102, applications that require a large amount of calculation, connectivity (connectivity), etc. It is also necessary to increase the speed (internal bandwidth) of various data flows such as image data and control commands. However, the parallel PCI bus has problems such as racing and skew. More specifically, the device 103 having the same function as the MCH (memory control hub) may refuse access from the port 1 or port 2 when a memory access from the CPU 101 occurs. The transfer of image data and other data between the devices 104 and 105 is hindered, and for example, the transfer of image data from the HDD 106 or the memory 10a7 to the network may be delayed. On the other hand, when access from port 1 or port 2 is not denied, there is a problem that the processing of the CPU 101 is hindered.

  Recently, the use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

  According to Patent Document 2, it is proposed to use PCI Express as an internal interface.

JP 2001-016382 A JP 2004-221809 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, even when PCI Express is used as an internal interface as proposed in Patent Document 2, there is a problem that must be solved.

  For example, in the configuration of the controller 300 as shown in FIG. 23, when memory access from the CPU 302 to the main memory 303 occurs in the device 301, image data and other data transfer between the device 304 and the device 305 are performed. There is a problem that is disturbed.

The present invention has been made in view of the above, and an object thereof is to provide a control device, an image processing system, and a data transfer path switching method that do not hinder image data and other data transfer between devices. .

In order to solve the above-described problems and achieve the object, a control device according to a first aspect of the present invention includes a root device connected to a processor and a memory and having a root function, and the root device via a first bus. A first device to be connected; and a second device connected to the root device via a second bus and connected to the first device via a third bus; The root device includes the first bus and the root device and the second device that connect the first device and the root device when the processor accesses the memory via the root device. the third connecting the first from said data transfer path between the first device of the second device via the second bus connecting bets A switching means for switching to a second data transfer path via the bus.

According to a second aspect of the present invention, in the control device according to the first aspect, the first device and the second device are switched from the first data transfer path to the second data transfer path. Each of the switches, and the switching means sends a signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path via the first bus. By transmitting to the first device and transmitting to the second device via the second bus, the first data transfer path is switched to the second data transfer path .

The invention according to claim 3 is the control device according to claim 1, wherein the first device and the second device are switched from the first data transfer path to the second data transfer path. And the switching means indicates the first device for causing the switch to perform control to switch from the first data transfer path to the second data transfer path as a communication destination. By transmitting a communication address to the second device and transmitting a communication address indicating the second device as a communication destination to the first device, the second data transfer from the first data transfer path Switch to a route .

According to a fourth aspect of the present invention, in the control device according to the first aspect, the first device and the second device are switched from the first data transfer path to the second data transfer path. Each of the switches, further comprising a first signal line different from the first bus for connecting the root device and the first device, and the root device and the second device, further comprising a different second signal line and the second bus for connecting said switching means to perform the control of switching from the first data transfer path to said second data transfer path to the switch A signal for transmitting to the first device via the first signal line and to the second device via the second signal line. Switch from the data transfer path to said second data transfer path.

According to a fifth aspect of the present invention, there is provided an image processing system connected to a processor and a memory, having a root function and having a control function for the memory, and being connected to the memory control device via a first bus. And an image processing controller that executes image processing and is connected to the memory control device via a second bus and to the image processing controller via a third bus to control the I / O device. An I / O control device, wherein the memory control device is positioned between the image processing controller and the I / O control device when the processor accesses the memory via the memory control device. It said first bus and said that the first bus to connect the memory control device Said third bus connecting the first data transfer path through the second bus for connecting the memory control device and the I / O control device and the image processing controller and said I / O control device There is a switching means for switching to the second data transfer path through.

According to a sixth aspect of the present invention, in the image processing system according to the fifth aspect , the image processing controller and the I / O control device are switched from the first data transfer path to the second data transfer path. A switch for switching the switching means from the first data transfer path to the second data transfer path via the first bus. By transmitting to the image processing controller and transmitting to the I / O control device via the second bus, the first data transfer path is switched to the second data transfer path .

The invention according to claim 7 is the image processing system according to claim 5 , wherein the image processing controller and the I / O device are switched from the first data transfer path to the second data transfer path. And the switching stage has a communication address indicating the image processing controller as a communication destination for causing the switch to perform control to switch from the first data transfer path to the second data transfer path. By transmitting to the I / O control device and a communication address indicating the I / O control device as a communication destination to the image processing controller, the first data transfer path is changed to the second data transfer path. Switch .

The invention according to claim 8 is the image processing system according to claim 5 , further comprising a first signal line different from the first bus connecting the root device and the image processing system, The switch further comprises a second signal line different from the second bus connecting the root device and the I / O control device, and the switching means connects the second data from the first data transfer path. A signal for causing the switch to perform control to switch to a transfer path is transmitted to the image processing controller via the first signal line and transmitted to the I / O control device via the second signal line. As a result, the first data transfer path is switched to the second data transfer path .

A data transfer path switching method according to a ninth aspect of the present invention is the data transfer path switching method executed by a root device connected to the processor and the memory and having a root function. accessing, when access to the memory by the processor is generated, the first bus connecting the first device connected via the first bus to the root device and the said root device and via said second bus connecting the second device connected via a third bus to the first device is connected via a second bus to the root device and the root device first from the data transfer path said first device and the third for connecting the second device to Switch to the second data transfer path through the scan.

The invention according to claim 10 is the data transfer path switching method according to claim 9 , wherein the first device and the second device are connected to the second data transfer path from the first data transfer path. Each of which is provided with a switch for switching to the second data transfer path from the first data transfer path via the first bus. By transmitting to the first device and transmitting to the second device via the second bus, the first data transfer path is switched to the second data transfer path .

The invention according to claim 11 is the data transfer path switching method according to claim 9 , wherein the first device and the second device are connected to the second data transfer path from the first data transfer path. Communication that indicates the first device for causing the switch to perform control to switch from the first data transfer path to the second data transfer path. An address is transmitted to the second device and a communication address indicating the second device as a communication destination is transmitted to the first device, whereby the second data transfer path is transmitted from the first data transfer path. Switch to .

The invention according to claim 12 is the data transfer path switching method according to claim 9 , wherein the first device and the second device are connected to the second data transfer path from the first data transfer path. Each of which has a switch for switching to the first data transfer path, and a signal for causing the switch to switch from the first data transfer path to the second data transfer path. Is transmitted to the first device via a first signal line that is different from the first bus that connects the first bus, and is different from the second bus that connects the root device and the second device. The first data transfer path is switched to the second data transfer path by transmitting to the second device via the second signal line .

Claim 1, according to the invention of 5,9, even when the memory access from the CPU occurs in root device, and the first and second devices directly connected by a second high-speed serial bus data By transferring data via the transfer path, it is possible to provide a control device that does not hinder image data and other data transfer between the first device and the second device.

Further, according to the inventions according to claims 2 , 6 and 10 , there is an effect that the data transfer path can be switched in accordance with a signal from the root device.

Further, according to the third , seventh , and eleventh aspects , the data transfer path can be switched according to the communication destination address of the packet.

According to the inventions of claims 4 , 8 , and 12 , data is transferred by transmitting a signal generated in the root device to the first device and the second device via the signal line. A path switching signal can be transmitted at high speed, and a data transfer path can be switched according to a signal from the root device.

  Exemplary embodiments of a control device, an image processing system, and a data transfer method according to the present invention are explained in detail below with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the [Image Processing System] column for the image processing system of the present embodiment. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected to the PCI bridge 119. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image processing system]
The image processing system such as a digital copying machine or MFP according to the present embodiment uses a PCI Express standard high-speed serial bus as described above for its internal interface.

  FIG. 16 is a schematic block diagram illustrating a configuration example of the control device 1 of the image processing system according to the present embodiment. The image processing system according to the present embodiment is applied to a device such as an MFP, for example. As components of the control device 1, a CPU 2 that controls the entire system, a main memory 3, and a memory having a root function A memory control hub 4 that is a control device, an I / O control hub 5 that is a second device and an I / O control device, and an image processing controller that is a first device and controls various processes in the MFP. An MFP controller 6, a memory 10a, and an HDD (Hard Disk Drive) 10b are provided.

  The memory control hub 4 corresponds to a PCI Express standard root complex (root device having a tree-structured root function), and controls the main memory 3 to be connected to the CPU 2 and the I / O control hub 5. Controls data transfer with connected I / O devices.

  The I / O control hub 5 controls a connected I / O device (for example, hard disk, graphics, network, etc.) or its interface.

  In this embodiment, the memory control hub 4 and the I / O control hub 5 are connected to each other by the PCI Express standard high-speed serial buses 7 and 8, respectively. Yes. By connecting the high-speed serial buses 7 and 8 in this way, the speed of data transfer (data transfer path A) from the I / O control hub 5 to the MFP controller 6 via the memory control hub 4 is increased.

  In addition, in this embodiment, the I / O control hub 5 and the MFP controller 6 are connected by a PCI Express standard high-speed serial bus 9 which is a second high-speed serial bus. That is, the control device 1 of the image processing system according to the present embodiment includes a data transfer path B in which the I / O control hub 5 and the MFP controller 6 are directly connected in addition to the data transfer path A via the memory control hub 4. Have.

  As shown in FIG. 17, the MFP controller 6 receives the signal 1 from the memory control hub 4 and changes the data transfer path from the data transfer path A to the I / O control hub 5 to the I / O control hub 5. A switch 11 for switching to the data transfer path B in which the / O control hub 5 and the MFP controller 6 are directly connected is provided. On the other hand, the I / O control hub 5 receives the signal 2 from the memory control hub 4 and transfers the data transfer path to the MFP controller 6 from the data transfer path A via the memory control hub 4 to the I / O control hub 5 and the MFP. A switch 12 for switching to a data transfer path B directly connected to the controller 6 is provided.

  In such a configuration, data transfer path switching control according to signals 1 and 2 from the memory control hub 4 will be described.

  When a memory access from the CPU 2 occurs in the memory control hub 4, the switch 11 of the MFP controller 6 and the switch 12 of the I / O control hub 5 are controlled by the signals 1 and 2 from the memory control hub 4. Data transfer is performed between the MFP controller 6 and the I / O control hub 5 via the data transfer path B in which the 6 and the I / O control hub 5 are directly connected. Here, route switching means is realized.

  As a result, even when a memory access from the CPU 2 occurs in the memory control hub 4, data is transferred via the data transfer path B in which the MFP controller 6 and the I / O control hub 5 are directly connected. It is possible to provide a data transfer system that does not hinder image data and other data transfer between 6 and the I / O control hub 5.

  As described above, according to the present embodiment, even when a memory access from the CPU 2 occurs in the memory control hub 4, data is transmitted via the data transfer path in which the MFP controller 6 and the I / O control hub 5 are directly connected. By transferring, it is possible to provide an image processing system that does not hinder the transfer of image data and other data between the MFP controller 6 and the I / O control hub 5, and to realize simultaneous parallel operation of the controller. it can.

  Further, the data transfer path can be switched in accordance with a signal from the memory control hub 4.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, when a memory access from the CPU 2 occurs in the memory control hub 4, the PCI Express standard high-speed serial bus 7 from the memory control hub 4 to the MFP controller 6 and the I / O control hub 5. , 8 to transmit the signals 1 and 2 to switch the data transfer path, but in this embodiment, the data transfer path is switched according to the communication destination address.

  FIG. 18 is a schematic block diagram illustrating a configuration example of the control device 1 of the image processing system according to the second embodiment of the present invention. As shown in FIG. 18, when the communication destination address is the I / O control hub 5, the MFP controller 6 sends a data transfer path to the I / O control hub 5 from the data transfer path A via the memory control hub 4. A switch 21 for switching to a data transfer path B in which the I / O control hub 5 and the MFP controller 6 are directly connected is provided. On the other hand, when the communication destination address is the MFP controller 6, the I / O control hub 5 transfers the data transfer path to the MFP controller 6 from the data transfer path A via the memory control hub 4 to the I / O control hub 5 and the MFP. A switch 22 for switching to the data transfer path B directly connected to the controller 6 is provided.

  In such a configuration, switching control of the data transfer path according to the communication destination address will be described.

  In this embodiment, the switch 21 of the MFP controller 6 and the switch 22 of the I / O control hub 5 are controlled by the communication destination address, and the data transfer path B in which the MFP controller 6 and the I / O control hub 5 are directly connected. Then, data transfer is performed between the MFP controller 6 and the I / O control hub 5. Here, the path switching means based on the communication destination address of the packet is realized.

  As a result, even when a memory access from the CPU 2 occurs in the memory control hub 4, data is transferred via the data transfer path B in which the MFP controller 6 and the I / O control hub 5 are directly connected. It is possible to provide a data transfer system that does not hinder image data and other data transfer between 6 and the I / O control hub 5.

  Thus, according to the present embodiment, the data transfer path can be switched according to the communication destination address.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, when a memory access from the CPU 2 occurs in the memory control hub 4, the PCI Express standard high-speed serial bus 7 from the memory control hub 4 to the MFP controller 6 and the I / O control hub 5. In this embodiment, a signal line is provided separately from the high-speed serial buses 7 and 8, and this signal line is connected to the data transfer path. The signals 1 and 2 are transmitted via the switch to switch the data transfer path.

  FIG. 19 is a schematic block diagram illustrating a configuration example of the control device 1 of the image processing system according to the third embodiment of the present invention. As shown in FIG. 19, in the control apparatus 1 of the image processing system of the present embodiment, in addition to the configuration described in the first embodiment, the memory control hub 4 and the I / O control hub 5 are arranged. The memory control hub 4 and the MFP controller 6 are connected by signal lines 31 and 32 provided separately from the high-speed serial buses 7 and 8, respectively. As a result, the signal 1 generated in the memory control hub 4 is transmitted to the MFP controller 6 via the signal line 31, and the signal 2 generated in the memory control hub 4 is transmitted via the signal line 32 to the I / O control. It is transmitted to the hub 5.

  Here, as shown in FIG. 20, the signal lines 31 and 32 transmit two states of “transfer permission to the memory control hub 4 (HIGH)” and “transfer disable to the memory control hub 4 (LOW)”. As a result, the switch 11 and the switch 12 are controlled, and the I / O control hub 5 and the MFP controller 6 via the high-speed serial bus 9 (data transfer path B) in which the MFP controller 6 and the I / O control hub 5 are directly connected. Transfer data to and from.

  As described above, according to the present embodiment, simple signal lines 31 and 32 are provided separately from the high-speed serial buses 7 and 8, and the signal 1 generated in the memory control hub 4 via these signal lines 31 and 32. , 2 are transmitted to the I / O control hub 5 and the MFP controller 6, a data transfer path switching signal can be transmitted at high speed.

  Further, as shown in FIG. 21, the I / O control hub 5 or the MFP controller 6 changes from “transfer permission to the memory control hub 4 (HIGH)” to “memory control hub 4” during data transfer with the memory control hub 4. When the status changes to “transfer impossible to (LOW)”, the data transfer with the memory control hub 4 is immediately stopped, and the high-speed serial bus 9 between the I / O control hub 5 and the MFP controller 6 ( Data transfer is performed via the data transfer path B). Thus, even when a memory access from the CPU 2 occurs in the memory control hub 4, image data and other data transfer between the I / O control hub 5 and the MFP controller 6 are not hindered.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is a schematic block diagram which shows the structural example of the control apparatus of the image processing system of the 1st Embodiment of this invention. It is explanatory drawing which shows the example of switching of the data transfer path | route in the control apparatus of an image processing system. It is explanatory drawing which shows the example of switching of the data transfer path | route in the control apparatus of the image processing system of the 2nd Embodiment of this invention. It is a schematic block diagram which shows the structural example of the control apparatus of the image processing system of the 3rd Embodiment of this invention. It is a timing chart which shows switch switching. It is a timing chart which shows data transfer switching. It is a block diagram which shows an example of the controller structure of the conventional image processing system. It is a block diagram which shows an example of the controller structure of the image processing system using the conventional PCI Express.

Explanation of symbols

1 control device 2 CPU
3 memory 4 root device, memory control device 5 second device, I / O control device 6 first device, image processing controller 7, 8 high-speed serial bus 9 second high-speed serial bus 11, 21 first device ( Image processing controller switch 12, 22 Second device (I / O control device) switch 31, 32 Signal line A Data transfer path via root device (memory control device) B Data transfer path

Claims (12)

A root device connected to the processor and memory and having a root function;
A first device connected to the root device via a first bus;
A second device connected to the root device via a second bus and connected to the first device via a third bus;
With
The root device includes the first bus and the root device and the second device that connect the first device and the root device when the processor accesses the memory via the root device. switching to said second data transfer path through said third bus connecting the first device and the second device from the first data transfer path via the second bus connecting bets Having switching means,
A control device characterized by that. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
The switching means transmits a signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path to the first device via the first bus. Switching from the first data transfer path to the second data transfer path by transmitting to the second device via the second bus ;
The control device according to claim 1. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
The switching means sets a communication address indicating the first device as a communication destination to the second device for causing the switch to perform control to switch from the first data transfer path to the second data transfer path. Transmitting the communication address indicating the second device as a communication destination to the first device, thereby switching from the first data transfer path to the second data transfer path .
The control device according to claim 1. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
A first signal line different from the first bus connecting the root device and the first device;
A second signal line different from the second bus connecting the root device and the second device;
The switching means transmits a signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path to the first device via the first signal line. And switching to the second data transfer path from the first data transfer path by transmitting to the second device via the second signal line .
The control device according to claim 1. A memory control device connected to the processor and the memory and having a root function and a control function for the memory;
An image processing controller connected to the memory control device via a first bus and executing image processing;
An I / O control device connected to the memory control device via a second bus and connected to the image processing controller via a third bus for controlling the I / O device;
With
The memory control device includes the first bus and the memory control located between the image processing controller and the I / O control device when the processor accesses the memory via the memory control device. The image processing controller and the I / O from a first data transfer path via the first bus connecting the device and the second bus connecting the memory control device and the I / O control device Switching means for switching to a second data transfer path via the third bus connecting the control device;
An image processing system characterized by that. The image processing controller and the I / O control device each have a switch for switching from the first data transfer path to the second data transfer path,
The switching means transmits a signal for causing the switch to perform control for switching from the first data transfer path to the second data transfer path to the image processing controller via the first bus, and Switching from the first data transfer path to the second data transfer path by transmitting to the I / O control device via a second bus;
The image processing system according to claim 5. The image processing controller and the I / O device each have a switch for switching from the first data transfer path to the second data transfer path,
The switching means provides the I / O control device with a communication address indicating the image processing controller as a communication destination for causing the switch to perform control to switch from the first data transfer path to the second data transfer path. Transmitting the communication address indicating the I / O control device as a communication destination to the image processing controller and switching from the first data transfer path to the second data transfer path.
The image processing system according to claim 5. A first signal line different from the first bus connecting the root device and the image processing system;
A second signal line different from the second bus for connecting the root device and the I / O control device;
The switching means transmits a signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path to the image processing controller via the first signal line. Switching from the first data transfer path to the second data transfer path by transmitting to the I / O control device via the second signal line;
The image processing system according to claim 5. In a data transfer path switching method executed by a root device connected to a processor and a memory and having a root function,
The processor accesses the memory via the root device;
The first bus and the root device that connect the root device to the first device connected to the root device via the first bus when the processor accesses the memory. first passing through the second bus connecting the second device connected via a third bus to the first device is connected via a second bus to the root device Switching from a data transfer path to a second data transfer path via the third bus connecting the first device and the second device;
A data transfer path switching method. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
A signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path is transmitted to the first device via the first bus and the second bus Switching from the first data transfer path to the second data transfer path by transmitting to the second device via
The data transfer path switching method according to claim 9. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
A communication address indicating the first device as a communication destination for causing the switch to perform control to switch from the first data transfer path to the second data transfer path is transmitted to the second device and the second device Switching from the first data transfer path to the second data transfer path by transmitting a communication address indicating the second device as a communication destination to the first device;
The data transfer path switching method according to claim 9. The first device and the second device are devices each having a switch for switching from the first data transfer path to the second data transfer path,
A signal for causing the switch to perform control to switch from the first data transfer path to the second data transfer path is different from the first bus that connects the root device and the first device. The second device via a second signal line that transmits to the first device via a single signal line and is different from the second bus that connects the root device and the second device. To switch from the first data transfer path to the second data transfer path,
The data transfer path switching method according to claim 9.

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