JP2005166027A - Image system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image apparatus system allowing an effective use such as the speedup of a PCI Express system serving as a high-speed serial I/F. <P>SOLUTION: In a tree structure of the PCI Express system, strongly correlated devices, for example, which are paired necessarily in data transfer, such as a memory 5j temporarily storing image data, a compressor 5i compressing the image data in the memory 5j into coded data, and a HDD 5k storing the compressed coded data are connected to the upstream side via a share switch 9. In this way, data can be transferred between and among the strongly correlated devices 5i, 5j, and 5k only by passing the data through the shared switch 9, and the speed of data transfer can be increased in comparison with a system passing data through a route complex. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image system used for various image forming processes, for example.

  Generally, in a device / system that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image equipment. The use of a high-speed serial interface is being considered in place of the system interface. Conventionally, there are standards such as IEEE1394 and USB as a widely used serial interface, but there are problems such as insufficient transfer rate and difficulty in securing a scalable bus width compared to PCI. . For this reason, the use of an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus system is being studied as another high-speed serial interface.

  The PCI Express system will be described in detail later, but schematically, for example, a tree structure (tree structure) such as root complex-switch (arbitrary hierarchy) -device as shown in FIG. ) Is configured as a data communication network.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, when such a PCI Express system is simply used, the path through the root complex located at the root of the tree structure is used for data transfer between devices, and the data transfer speed cannot be increased. Yes, it may not be possible to say that the PCI Express functions are fully utilized.

  More specifically, according to the configuration using the route through the root complex, when multiple data transfers are performed simultaneously, in the switch located between the device and the root complex, it is easy for contention to occur at the output port, and the transfer The rate is likely to drop. Such a decrease in the data transfer rate is the same not only in the case of data transfer path contention but also in the case of a data transfer path that passes through more than necessary switches, but according to the configuration that uses the path through the root complex, However, there are many cases of passing through multi-stage switches, and there is a concern that the transfer rate is lowered.

  An object of the present invention is to provide an image system that can be effectively used, such as a higher speed PCI Express system that is a high-speed serial interface.

  More specifically, to improve data transfer efficiency by avoiding data transfer path contention when processing multiple independent data transfers in parallel, and data transfer paths that go through more stages than necessary. It is.

  The invention described in claim 1 is an image system using a high-speed serial interface system in which a communication channel independent of transmission and reception is established point-to-point as a data communication network using a tree structure, and is used as an end point on the downstream side in the tree structure Among a plurality of positioned devices, devices having strong correlations are connected to the upstream side through a common switch.

  According to a second aspect of the present invention, in the image system according to the first aspect, the high-speed serial interface system is a PCI Express system.

  According to a third aspect of the present invention, in the image system according to the first or second aspect, a memory that temporarily stores image data in a plurality of devices, and a compressor that compresses the image data in the memory into code data The hard disk drive that stores the compressed code data is a highly correlated device.

  According to a fourth aspect of the present invention, in the image system according to the first or second aspect, the hard disk drive that stores the compressed code data in a plurality of devices, and the decompression that expands the code data on the hard disk drive into image data. A device and a memory in which decompressed image data is expanded are devices having a strong correlation.

  According to a fifth aspect of the present invention, in the image system according to the first or second aspect, the memory for temporarily storing the image data in the plurality of devices, the image data is compressed into the code data, and the code data is converted into the image data. A compression / expansion device that decompresses and a hard disk drive that stores compressed code data are devices having a strong correlation.

  According to a sixth aspect of the present invention, there is provided an image system according to the first or second aspect, wherein a memory for temporarily storing image data in a plurality of devices and a rotator for performing rotation processing on the image data are correlated. Use strong devices.

  According to a seventh aspect of the present invention, in the image system according to the first or second aspect, among the plurality of devices, an input unit for inputting image data, and a device having a compression function for compressing the input image data into code data A device that temporarily stores the compressed code data is a device having a strong correlation.

  According to an eighth aspect of the present invention, in the image system according to the seventh aspect of the present invention, a magnification changer for enlarging / reducing the image data is provided between devices having a strong correlation.

  The invention according to claim 9 is the image system according to claim 1 or 2, wherein in the plurality of devices, a memory in which the compressed code data is expanded, and a decompression function for decompressing the code data on the memory into the image data And a device that outputs a print based on the decompressed image data are devices having a strong correlation.

  According to a tenth aspect of the present invention, in the image system according to the ninth aspect, a magnification changer for enlarging / reducing the expanded image data is provided between devices having a strong correlation.

  According to an eleventh aspect of the present invention, in the image system according to the first or second aspect, a memory that temporarily stores image data and print data in a plurality of devices, and the image data and print data on the memory are combined. The synthesizer that performs the output and the output unit that prints out based on the combined data are devices having strong correlation.

  According to a twelfth aspect of the present invention, in the image system according to the first or second aspect, a memory in which the code data compressed in the printer language is expanded in a plurality of devices, and the code data on the memory is translated to generate an image. A data converter that develops data and an output unit that prints out data based on the developed image data are devices having a strong correlation.

  According to the present invention, as shown in claims 3 to 12, a device having a strong correlation, such as a natural pairing in data transfer, is used as a data communication network with a tree structure, and is a point-to-point independent communication. Since a high-speed serial interface system that establishes a channel, for example, a tree structure based on a PCI Express system, is connected to the upstream side via a common switch, data transfer between these highly correlated devices is performed only through the common switch. Therefore, it is possible to avoid contention of the output port of the switch as much as possible, or to reduce the number of switches via the switch as much as possible, and to further increase the data transfer speed as compared with the case of passing through the root complex. .

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 117
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7 (a), the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7 (b), Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image system]
The image system according to the present embodiment uses the PCI Express system as described above, particularly with the tree structure improved.

  FIG. 15 is a principle schematic diagram showing an example of a tree structure in the image system of the present embodiment. In the present embodiment, for example, two image devices 1 and 2 having different specifications are provided, and these image devices 1 and 2 are arranged with the switches 3 and 4 on the PCI Express system as the highest level. A tree structure in which a plurality of constituent devices are connected to the end point position. Of these image devices 1 and 2, the image device 1 is, for example, a high-speed image device, and the device 5 that is a component of the image device 1 is, for example, a control unit 5a, an input unit 5b, and an output unit 5c. , A rotator 5d, an image processor 5e, a data converter 5f, an image synthesizer 5g, an expander 5h, a compressor 5i, a memory 5j, an HDD 5k, etc., each connected to the switch 3 with a desired number of lanes (number of ports) Has been. The image device 2 is, for example, a low-speed image device, and the device 6 that is a component of the image device 2 includes, for example, a control unit 6a, an input unit 6b, an output unit 6c, a storage 6d, a switch 6e, and the like. It is connected to the switch 4 by the number of lanes (number of ports).

  Here, in the device, the input unit means, for example, a scanner engine that reads a document image with a CCD and converts it into an electrical signal. The output unit means a printer engine or the like that prints out paper or other recording material based on image data or the like. The storage is a memory that temporarily stores image data, or is used for storing image data or for jam backup, and means a memory, an HDD, or the like. The compressor compresses data, and the decompressor decompresses data. A compression / decompressor having both functions may be used. The rotator rotates image data by 90 °, 180 ° or 270 °. For example, when two A4 originals are aggregated and printed on A4 size paper, the print image is oriented in the direction of the paper in the tray. Used when matching. The data converter is a part that performs processing for developing, for example, a printer language. The image synthesizer is a part that performs a process of combining image data and print data into one data, for example.

  An image system 8 is configured by connecting the uppermost switches 3 and 4 constituting these image devices 1 and 2 to a common root complex 7 located at a higher level (base side).

  According to such a configuration, since the PCI Express system, which is a high-speed serial bus, is used, the data transfer speed can be basically increased. In addition, the data in each of the image devices 1 and 2 can be increased. Further speeding up of the transfer can be achieved. That is, the PCI Express systems in the image devices 1 and 2 are connected in a tree structure with the switches 3 and 4 as the highest level without going through the root complex, and between the devices 5a to 5k and 6a to 6e. Since the data transfer is performed without going through the root complex, high-speed processing becomes possible.

  Here, in the present embodiment, for example, in a plurality of devices 5a to 5k in the image device 1, a memory 5j that temporarily stores image data, and a compressor that compresses the image data in the memory 5j into code data. 5i and the HDD 5k that stores the compressed code data are devices having a strong correlation with each other, and have a tree structure connected to the upstream switch 3 via the common switch 9.

  FIG. 16 is a schematic block diagram showing extracted device parts having a strong correlation. The image data 10 stored in the memory 5j is compressed for jam backup and stored as code data 11 in the HDD 5k. Most of the operation modes are used, and the memory involved in such data transfer is used. The devices 5j, the compressor 5i, and the HDD 5k are devices having extremely strong correlations.

  Since devices having such a strong correlation are connected to one common switch 9 without going through the root complex, the image data 10 on the memory 5j is transferred to the compressor 5i via the common switch 9, After compression into code data by the compressor 5i, the code data can be stored in the HDD 5k for jam backup again by transferring to the HDD 5k via the common switch 9 (the arrow in FIG. 16 indicates the data flow). Is shown). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  In the present embodiment, the example of application to the case of the image system 8 in which the image devices 1 and 2 are systemized by the root complex 7 has been described. However, this is a case of a system configuration with a single configuration for only one image device. However, the same can be applied. Although the common switch 9 is connected to the switch 3, the common switch 9 may be connected to the root complex 7 in the same manner as the switch 3 as an equivalent to the switch 3.

  Further, combinations of strongly correlated devices connected to one common switch are not limited to the examples shown in FIGS. 15 and 16 but include various examples. Some examples will be described below.

  FIG. 17 is a schematic block diagram illustrating an example in which the memory 5j, the decompressor 5h, and the HDD 5k are connected to the common switch 12 as devices having a strong correlation.

  The code data 11 on the HDD 5k is decompressed into image data by the decompressor 5h and expanded in the memory 5j, and is used for print output or the like in most operation modes. The HDD 5k, the decompressor 5h, and the memory 5j that are involved are extremely strongly correlated devices.

  Since devices having such a strong correlation are connected to one common switch 12 without passing through the root complex, the code data 11 on the HDD 5k is transferred to the decompressor 5h via the common switch 12, After decompressing to image data by the decompressor 5h, the image data can be expanded again by transferring it to the memory 5j via the common switch 12 (arrows in FIG. 17 indicate the flow of data). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  FIG. 18 is a schematic block diagram illustrating an example in which the memory 5j, the compression / decompression unit 5m, and the HDD 5k are connected to the common switch 13 as devices having strong correlations. That is, the case of FIG. 16 and the case of FIG. 17 are combined, and this is an example in which a combined compression / expansion device 5m is used instead of the compressor 5i and the expansion device 5h.

  Since devices having such a strong correlation are connected to one common switch 13 without going through the root complex, the image data 10 on the memory 5j is transferred to the compression / decompression device 5m via the common switch 13. Then, after being compressed into code data by the compression / decompression unit 5m, the code data can be stored in the HDD 5k for jam backup by being transferred again to the HDD 5k via the common switch 13. Conversely, the code data 11 on the HDD 5k is transferred to the compression / decompression device 5m via the common switch 13, decompressed into image data by the compression / decompression device 5m, and then again transferred to the memory 5j via the common switch 13. The image data can be expanded by transferring. Since data transfer in any case can be performed without going through the root complex, extremely high-speed processing is possible.

  FIG. 19 is a schematic block diagram illustrating an example in which the memory 5j and the rotator 5d are connected to the common switch 14 as devices having a strong correlation.

  There are many cases where the image data 10 on the memory 5j is rotated in the output direction and developed again on the memory 5j. Therefore, the memory 5j and the rotator 5d involved in such data transfer are devices having a very strong correlation. It is between each other.

  In the illustrated example, the image data 10 (R1, R2) for two A4 originals on the memory 5j is reduced to A5 size and expanded on the memory 5j, and then transferred to the rotator 5d via the common switch 14. In this example, each 90 ° rotation process is performed and transferred to the memory 5j via the common switch 14 again to be consolidated into one A4 document. Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing is possible.

  In FIG. 20, a memory 5j, a scanner engine 5n, which is an example of an input unit, and a compression / decompression device 5m (which only needs to have a compression function and may be a compression device 5i) are connected to the common switch 15 as devices having a strong correlation. It is a schematic block diagram which shows an example.

  Since image data read by the scanner engine 5n is often compressed and expanded on the memory 5j, the scanner engine 5n, the compression / decompression device 5m, and the memory 5j involved in such data transfer are extremely correlated. Strong devices.

  Since the devices having such a strong correlation are connected to one common switch 15 without going through the root complex, the image data 10 read by the scanner engine 5n is compressed via the common switch 15 to the compression / decompression device 5m. The image data can be expanded by being transferred to the memory 5j via the common switch 15 after being compressed into the code data by the compression / decompression unit 5m (the arrows in FIG. 20 indicate the data flow). ing). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  In this case, as shown in FIG. 21, a zooming device 5o for performing scaling processing for enlarging / reducing the image data 10 read by the scanner engine 5n may be included among devices having a strong correlation.

  FIG. 22 shows a common switch 16 in which a memory 5j, a plotter engine 5p as an example of an output unit, and a decompressor 5h may be used as long as they have a decompression function and may be a decompressor 5h). It is a schematic block diagram which shows the example connected to.

  Since the code data 11 developed on the memory 5j is decompressed and printed out by the plotter engine 5p in many cases, the memory 5j involved in such data transfer, the compression / decompression device 5m, and the plotter engine 5p are extremely correlated. Are strong devices.

  Since devices having such a strong correlation are connected to one common switch 15 without going through the root complex, the code data 11 expanded in the memory 5j is transferred to the compression / decompression device 5m via the common switch 16. The image data 10 is transferred, decompressed to the image data 10 by the compression / decompression unit 5m, and transferred to the plotter engine 5p via the common switch 16, whereby the image data 10 can be printed out (the arrow in FIG. 21 indicates the data flow). Is shown). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  In this case, as shown in FIG. 23, a scaling unit 5o that performs scaling processing for enlarging / reducing the image data 10 expanded by the compression / decompression unit 5m may be included in devices having a strong correlation.

  FIG. 24 is a schematic block diagram showing an example in which the memory 5j, the plotter engine 5p as an example of the output unit, and the image synthesizer 5g are connected to the common switch 17 as devices having strong correlations.

  In many cases, the image data 10 stored in the memory 5j and the print data 18 such as “confidential” are synthesized by the image synthesizer 5g and printed out by the plotter engine 5p. The memory 5j, the image synthesizer 5g, and the plotter engine 5p that are involved in the above are devices having extremely strong correlation.

  Since devices having such a strong correlation are connected to one common switch 17 without going through the root complex, the image data 10 and the print data 18 stored in the memory 5j are connected via the common switch 17. The image data is transferred to the image synthesizer 5g, and the image synthesizer 5g synthesizes these data. The image data is transferred to the plotter engine 5p via the common switch 17 to print out the image data 10 and the print data 18 combined. (Arrows in FIG. 24 indicate the flow of data). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  FIG. 25 is a schematic block diagram showing an example in which the memory 5j, the plotter engine 5p as an example of the output unit, and the data converter 5f are connected to the common switch 19 as devices having strong correlations.

  In many cases, the code data 11 (printer language) developed on the memory 5j is translated by the data converter 5f and printed out as image data 10 by the plotter engine 5p. The data converter 5f and the plotter engine 5p are devices having extremely strong correlation.

  Since devices having such a strong correlation are connected to one common switch 19 without going through the root complex, the code data 11 developed on the memory 5j is transferred to the data converter 5f via the common switch 19. , The image data 10 is translated by the data converter 5f, and transferred to the plotter engine 5p via the common switch 19. The arrow in FIG. 25 indicates the data flow. Is shown). Since data transfer in this case can be performed without going through the root complex, extremely high-speed processing becomes possible.

  The present invention is not limited to these examples, and various combinations can be taken.

[Discussion about effects]
FIG. 26 schematically shows a configuration example as described above as a configuration example on the tree structure of PCI Express, in contrast to the conventional example. Here, A, B, C, a, b, and c exist as devices, devices A, B, and C, devices a, b, and c have strong correlations, and switch SW1 exists on the upstream side. Assume that the switches SW2 and SW3 exist on the downstream side, and the devices A, B, C, a, b, and c exist on the downstream side. Under such a premise, FIG. 26 (a) shows a conventional configuration example, in which the devices A, B, C, a, b, and c are connected to the upper switches SW2 and SW3 regardless of their correlation. System configuration. Therefore, in such a system configuration, when data transfer is performed in the order of device A → device B → device C, a data transfer path of device A → switch SW2 → device B → switch SW2 → switch SW1 → switch SW3 → device C is obtained. It goes through a four-stage switch. When data is transferred in the order of device a → device b → device c, the data transfer path is device a → switch SW2 → switch SW1 → switch SW3 → device b → switch SW3 → device c and passes through four stages of switches. It will be. Further, when these two systems of data transfer are performed simultaneously, the output ports compete at three locations of the switches SW2, SW1, and SW3.

  On the other hand, FIG. 26 (b) shows a configuration example of the present plan, in which devices are grouped together with strongly correlated devices, that is, devices A, B, C, devices a, b, c, and switches SW2, SW3 is a common switch, and devices A, B, and C are connected to the common switch SW2, while devices a, b, and c are connected to the common switch SW3. Therefore, in such a system configuration, when data transfer is performed in the order of device A → device B → device C, the data transfer path becomes device A → switch SW2 → device B → switch SW2 → device C and passes through a two-stage switch. Will be. Further, when data is transferred in the order of device a → device b → device c, the data transfer path becomes device a → switch SW3 → device b → switch SW3 → device c, and passes through a two-stage switch. Further, even when these two systems of data transfer are performed simultaneously, there is no contention for the switch output port.

  Therefore, consider the effect of switch output port contention. When a conflict occurs in the output port in the PCI Express switch, the data transfer rate is lowered. In FIG. 27, under the condition that there is one output port for four input ports in the PCI Express switch, four different types of traffic are started at the same time, and data transfer is completed in order according to the transfer rate. It is the graph which showed the characteristic in the case of going. In the figure, the horizontal axis represents the transfer time, the vertical axis represents the data transfer amount (integrated value) of each port, and the slope of each graph represents the transfer rate. Note that the payload size (meaning the size of the data portion other than the header information out of the total packet data size) is a measurement example under the condition that all four types are fixed to 64 bytes. The data transfer algorithm is a weighted round robin (WRR) in the PCI Express standard, and shows an example of characteristics when data transfer is set at a ratio of 1: 2: 4: 8 for four types. When the data transfer of one traffic class is completed, the algorithm is to transfer data while changing the ratio, such as 8: 4: 2 and further 8: 4 for the remaining traffic classes.

  In FIG. 27, it can be seen that, from the left, four transfers are in conflict, three transfers are in conflict, two transfers are in conflict, and there is no conflict. Here, it can be seen that as the number of competing traffics decreases, the slope of each graph, that is, the transfer rate becomes steep, and the data transfer rate improves. In this regard, according to the present embodiment as described above, since the devices having strong correlation are connected to the upstream side via the common switch, the connection relation to the switch is summarized. It can be seen that even when it is performed, contention of the output port of the switch can be avoided and the data transfer rate can be improved.

  Next, consider the effect of the number of switch stages. When data is divided and transferred by a certain amount (for example, when image data is transferred to a plotter in the image forming system by dividing it into one line in the main scanning direction), the packet data is transmitted from the transmission source to the transmission destination. The influence of the initial delay that reaches the point becomes larger with the number of switch stages through which it passes.

  FIG. 28 is a graph showing the relationship between the payload size and the transfer rate, using the number of switches (number of stages) passed through as a parameter in the data transfer path, and the influence of the number of switches (number of stages) passed through on the transfer rate. I understand. In the figure, in order from the top, there is no timing constraint, the switch has one stage, the delay structures 1, 2, 3, the switch has two stages, the delay structures 1, 2, 3, the switch has three stages, and the delay structures 1, 2, 3, The case where there are four stages of delay structures 1, 2, 3 and five switches of delay structures 1, 2, 3 is shown. Each time the number of switches passing through increases by one, the packet transfer delay time is added. The larger the packet data size, the greater the delay. For this reason, it can be seen that when there are a plurality of stages of switches on the data transfer path, the data transfer rate decreases as the size of data transmitted in one packet increases. In this regard, according to the present embodiment, since the devices having strong correlation are connected to the upstream side via the common switch, the connection relation to the switch is summarized, so that the number of stages of switches that pass through on the data transfer path It can be seen that the decrease in the data transfer rate can be suppressed.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. It is a principle schematic diagram which shows the example of a tree structure in the imaging device system of this Embodiment. It is a schematic block diagram which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. It is a schematic block diagram of the modification which extracts and shows the device part with a strong correlation. (A) is a schematic diagram schematically showing a configuration example on the PCI Express tree structure in the case of the conventional method, and (b) is schematically showing a configuration example on the PCI Express tree structure in the case of the present invention method. It is a schematic diagram. 4 is a graph showing characteristics when four different types of traffic are simultaneously started in a PCI Express switch, and data transfer is sequentially terminated according to the transfer rate. 6 is a graph showing the relationship between the payload size and the transfer rate, with the number of switches (number of stages) passing through the data transfer path as a parameter.

Explanation of symbols

5,6 Device 9,12-17,19 Common switch

Claims (12)

An image system using a high-speed serial interface system in which a communication channel independent of transmission and reception is established point-to-point as a data communication network using a tree structure,
An image system characterized in that among a plurality of devices located at a downstream end point in the tree structure, devices having a strong correlation are connected to an upstream side through a common switch.   The image system according to claim 1, wherein the high-speed serial interface system is a PCI Express system.   Among a plurality of devices, a memory that temporarily stores image data, a compressor that compresses image data in the memory into code data, and a hard disk drive that stores compressed code data are strongly correlated with each other. The image system according to claim 1, wherein the image system is an image system.   A device having a strong correlation between a hard disk drive for storing compressed code data, a decompressor for expanding the code data on the hard disk drive into image data, and a memory in which the decompressed image data is expanded, among a plurality of devices The image system according to claim 1, wherein the image system is a pair.   Among a plurality of devices, a memory that temporarily stores image data, a compression / decompressor that compresses the image data into code data and decompresses the code data into image data, and a hard disk drive that stores the compressed code data The image system according to claim 1, wherein the devices are highly correlated with each other.   The image according to claim 1 or 2, wherein among a plurality of devices, a memory for temporarily storing image data and a rotator for performing rotation processing on the image data are mutually correlated devices. system.   Among a plurality of devices, a device having a strong correlation between an input unit for inputting image data, a device having a compression function for compressing input image data into code data, and a memory for temporarily storing the compressed code data The image system according to claim 1, wherein the image system is a pair.   The image system according to claim 7, further comprising: a power changer that enlarges / reduces image data between devices having strong correlation.   A memory in which compressed code data is expanded in a plurality of devices, a device having a decompression function for decompressing the code data on the memory into image data, and an output unit for printing out based on the decompressed image data The image system according to claim 1, wherein the devices are highly correlated with each other.   The image system according to claim 9, further comprising a power changer that enlarges / reduces the expanded image data between devices having a strong correlation.   Correlating memory that temporarily stores image data and print data, a combiner that combines image data and print data on the memory, and an output unit that prints output based on the combined data in multiple devices The image system according to claim 1, wherein the devices are strong devices. Among a plurality of devices, a memory in which code data compressed into a printer language is expanded, a data converter that translates the code data in the memory and expands the image data, and prints out based on the expanded image data The image system according to claim 1, wherein the output unit is a highly correlated device.

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